Woogeun Rhee received the B.S. degree in electronics engineering from Seoul National University, Seoul, Korea, in 1991, the M.S. degree in electrical engineering from the University 0f California, Los Angeles, in 1993, and the Ph.D. degree in electrical and computer engineering from the University 0f
Illinois, Urbana-Champaign, in 2001.
From 1997 to 2001, he was with Conexant Systems, Newport Beach , CA , where he was a Principal Engineer and mainly involved in the development of low-power low-cost fractional-N synthesizers. From 2001 to 2006, he was with IBM Thomas J. Watson Research Center , Yorktown Heights , NY and worked on clocking area for high-speed I/O serial links, including low-jitter PLLs, clock-and-data recovery circuits, and on-chip testability circuits. In August 2006, he joined the faculty of the Institute of Microelectronics at Tsinghua University, Beijing , China , where he is currently an Associate Professor. Since December 2008, he also has been an Adjunct Professor of the Shanghai Research Institute of Microelectronics at Peking University, China. His research interests are in versatile clocking systems for high speed I/O interfaces and in high performance RF front-end systems with emphasis on wideband fractional-N frequency synthesizer design. He has 12 U.S. patents issued in clocking and frequency generation areas.
Dr. Rhee has served as an Associate Editor for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART–II: EXPRESS BRIEFS and a technical program subcommittee member for Asian Solid-State Circuits Conference (A-SSCC) and International Symposium on VLSI Design, Automation, and Test (VLSI-DAT) since 2008. He was the recipient of the IBM Faculty Award in 2007 from IBM Corporation, USA and listed in Marquis Who’s Who in the World 2009/2010.
High-performance fractional-N frequency synthesizer design for wireless
Low-cost and robust clocking system design for I/O serial links
Low-power transceiver design for wireless body area network (WBAN) and wireless sensor network (WSN)
On-chip testability & diagnosis for robust SoC design
PLL Design and Clock/Frequency Generation
Institute of Microelectronics , Tsinghua University , Beijing , 100084, P.R. China