Publications

 

¡ì Journals/Book Chapters

1. Y. Sun, J. Qiao, X. Yu, W. Rhee, B.-H. Park, and Z. Wang, ¡°A Continuously Tunable Hybrid LC-VCO PLL With Mixed-Mode Dual-Path Control and Bi-Level Delta-Sigma Modulated Coarse Tuning,¡± accepted for IEEE Trans. on Circuits and Systems I.

2. X. Yu, W. Rhee, and Z. Wang, ¡°DS phase-locked loops,¡± to appear in Integrated Microsystems, CRC Press.

3. Y. Sun, X. Yu, W. Rhee, D. Wang, and Z. Wang, ¡°A fast settling dual-path fractional-N PLL with hybrid-mode dynamic bandwidth control,¡± in IEEE Microwave and Wireless Components Letters (MWCL), vol. 20, no. 8, pp. 462-464, Aug. 2010.

4. Y. Sun, X. Yu, W. Rhee, S. Ko, W. Choo, B.-H. Park, and Z. Wang, ¡°Dual-path LC VCO design with partitioned coarse-tuning control in 65 nm CMOS,¡± in IEEE Microwave and Wireless Components Letters (MWCL), vol. 20, pp. 169-171. Mar. 2010.

5. L. Zhang, X. Yu, Y. Sun, W. Rhee, D. Wang, Z. Wang, and H. Chen, ¡°A hybrid spur compensation technique for finite-modulo fractional-N phase-locked loops,¡± in IEEE Journal of Solid-State Circuits, pp. 2922-2934, Nov. 2009. <Listed in Top 100 Documents Accessed among All IEEE Publications, Nov. 2009>

6. X. Yu, Y. Sun, W. Rhee, and Z. Wang, ¡°An FIR-embedded noise filtering method for DS fractional-N PLL clock generators,¡± in IEEE Journal of Solid-State Circuits, vol. 44, pp. 2426-2436,Sept. 2009. <Listed in Top 100 Documents Accessed among All IEEE Publications, Sept. 2009>

7. X. Yu, Y. Sun, W. Rhee, H. Ahn, B. Park, and Z. Wang, ¡°A DS fractional-N frequency synthesizer with customized noise shaping for WCDMA/HSDPA applications,¡± in IEEE Journal of Solid-State Circuits, vol. 44, pp. 2193-2201,Aug. 2009.

8. W. Rhee, H. Ainspan, D. Friedman, T. Rasmus, S. Garvin, and C. Cranford, ¡°A continuously tunable LC-VCO PLL with bandwidth linearization techniques for PCI Express Gen-2 Applications,¡± Journal of Semiconductor Technology and Science , vol. 8, pp.200-209, Sept. 2008

9. W. Rhee, K. Jenkins, J. Liobe, and H. Ainspan, ¡°Experimental analysis of substrate noise effect on PLL performance,¡± IEEE Transactions on Circuits and Systems II , vol. 55, pp. 638-642, July 2008

10. B. Soltaniaan, H. Ainspan, W. Rhee, D. Friedman, and P. Kingnet, ¡°An ultra compact differentially tuned 6-GHz CMOS LC VCO with dynamic common-mode feedback,¡± in IEEE Journal of Solid-State Circuits, vol. 42, pp. 1635-1641, Aug. 2007

11. J. Bulzacchelli, et al, ¡°A 10Gb/s 5-tap FFE transceiver in 90-nm CMOS technology,¡± in IEEE Journal of Solid-State Circuits , vol. 41, pp. 2885-2900, Dec. 2006

12. T. Beukema, et al, ¡°A 6.4Gb/s CMOS SerDes core with feedforward and decision feedback equalization,¡± in IEEE Journal of Solid-State Circuits , vol. 40, pp. 2633-2645, Dec. 2005

13. W. Rhee, B. Parker, and D. Friedman, ¡°A semidigital delay-locked loop using an analog-based finite state machine,¡± in IEEE Transactions on Circuits and Systems II , vol. 50, pp. 635-639, Nov. 2004

14. W. Rhee, ¡°Practical design aspects in fractional- N frequency synthesis,¡± Analog Circuit Design, Edited by A. van Roermund, M. Steyaert, and J. Huijsing, Kluwer Academic Publishers , pp. 3-26, 2003

15. W. Rhee, B. Song, and A. Ali, ¡°A 1.1-GHz CMOS fractional- N frequency synthesizer with a 3-b third-order delta-sigma modulator,¡± Phase-Locking in High Performance Systems: From Devices to Architectures, Edited by B. Razavi, John Wiley & Sons, Inc ., pp. 596-602, 2003

16. R. Magoon, A. Molnar, J. Zachan, G. Hatcher, and W. Rhee, ¡°A single-chip quad-band (850/900/1800/1900MHz) direct conversion GSM/GPRS RF transceiver with integrated VCOs and fractional-N synthesizer,¡± in IEEE Journal of Solid-State Circuits, vol. 37, pp. 1710-1720, Dec. 2002

17. W. Rhee, B. Bisanti, and A. Ali, ¡°An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with <10-Hz RF carrier resolution,¡± in IEEE Journal of Solid-State Circuits , vol. 37, pp. 515-520, Apr. 2002

18. W. Rhee, B. S. Song, and A. Ali, ¡°A 1.1-GHz CMOS fractional- N frequency synthesizer with a 3-b third-order delta-sigma modulator,¡± in IEEE Journal of Solid- State Circuits , vol. 35, pp. 1453-1460, Oct. 2000

19. D. Wilson, W. Rhee, and B. S. Song, ¡°Integrated RF receiver front ends and frequency synthesizers for wireless,¡± Emerging Technologies: Designing Low Power Digital Systems, Tutorial Workshops in IEEE International Symposium on Circuits and Systems (ISCAS) , pp. 369-396, June, 1996

¡ì Conferences

 

1. Z. Zhang, W. Rhee, and Z. Wang, ¡°A wide-tuning quasi-type-I PLL with voltage-mode frequency acquisition aid,¡± accepted for IEEE International Symposium on Circuits and Systems (ISCAS), May, 2011.

 

2. H. Lv, B. Zhou, W. Rhee, Y. Li, and Z. Wang, ¡°A relaxation oscillator with multi-phase triangular waveform generation,¡± accepted for IEEE International Symposium on Circuits and Systems (ISCAS), May, 2011.

 

3. J. Li, B. Zhou, Y. Sun, W. Rhee, and Z. Wang, ¡°Reconfigurable, spectrally efficient, high data rate IR-UWB transmitter design using a D-S PLL driven ILO and a 7-tap FIR filter,¡± accepted forInternational Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2010.

 

4. Y. Liu, N. Xu, W. Rhee, Z. Wang, and Z. Wang, ¡°Power and jitter optimized VCO design using an on-chip supply noise monitoring circuit,¡± in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Dec. 2010, pp. 939-942.

 

5. J. Li, N. Xu, Y. Sun, W. Rhee, and Z. Wang, ¡°Reconfigurable, fast AFC technique using code estimation and binary search algorithm for 0.2-6GHz SDR frequency synthesis,¡± in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Dec. 2010, pp. 1135-1138.

 

6. W. Rhee, N. Xu, B. Zhou, and Z. Wang, ¡°Low power, non invasive UWB systems for WBAN and biomedical applications,¡± in Proc. International Conference on ICT Convergence (ICTC), Nov. 2010, pp. 35-40.

 

7. B. Zhou, R. He, J. Qiao, J. Liu, W. Rhee, and Z. Wang, ¡°A low data rate FM-UWB transmitter with D-S based sub-carrier modulation and quasi-continuous frequency-locked loop,¡± in Proc. IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2010, pp. 33-36.

 

8. R. He, C. Liu, X. Yu, W. Rhee, J.-Y. Park, C. Kim, and Z. Wang, ¡°A low-cost, leakage-insensitive semi-digital PLL with linear phase detection and FIR-embedded digital frequency acquisition,¡± in Proc. IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2010, pp. 197-200.

 

9. Z. Zhang, J. Li, Y. Sun, W. Rhee, and Z. Wang, ¡°A digitally reconfigurable auto amplitude calibration method for wide tuning range VCO design,¡± in Proc. IEEE International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), Nov. 2010, pp. 542-544.

 

10. J. Li, N. Xu, W. Rhee, and Z. Wang, ¡°A -131dBc@1M phase noise,74% spectral efficiency, GA Optimized FIR impulse radio UWB transmitter,¡± in Proc. Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia), Sept. 2010, pp. 384-387.

 

11. C. Liu, H. Rui, X. Yu, W. Rhee, and Z. Wang, ¡°A latency-proof quantization noise reduction method for digitally-controlled ring oscillators,¡± in Proc. IEEE Midwest Symp. on Circuits and Systems (MWSCAS), Aug. 2010, pp. 97-100.

 

12. Y. Sun, X. Yu, W. Rhee, S. Ko, W. Choo, B. Park, and Z. Wang, ¡°Low-noise fractional-N PLL design with mixed-mode triple-input LC VCO in 65nm CMOS,¡± in Proc. IEEE RFIC Symposium, May 2010, pp. 61-64.

 

13. X. Yu, J. Qiao, W. Rhee, J. Park, K. Lee, and Z. Wang, ¡°A semi-digital cascaded CDR with fast phase acquisition and adaptive resolution control,¡± to appear in Proc. International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2010, pp. 307-310.

 

14. Y. Sun, J. Qiao, J. Li, R. He, C. Liu, W. Rhee, S. H. Woo, and Z. Wang, ¡°A low-cost, multi-standard ¦¤¦² fractional-N synthesizer design for WiMAX/WLAN applications,¡± in Proc. International SoC Design Conference (ISOCC), Nov. 2009, pp. 100-103.

 

15. X. Yu, Y. Sun, W. Rhee, S. Ko, W. Choo, B.-H. Park, and Z. Wang, ¡°A 65nm CMOS 3.6GHz fractional-N PLL with 5th-order delta-sigma modulation and weighted FIR Filtering,¡± in Proc. IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2009, pp. 77-80.

 

16. J. Li, W. Rhee, and Z. Wang, ¡°Dual-carrier IR-based UWB transmitter with improved spectral efficiency,¡± in Proc. International Conference on Communications, Circuits and Systems (ICCCAS), July 2009, pp. 788-792.

 

17. R. He, J. Li, W. Rhee, and Z. Wang, ¡°Transient analysis of nonlinear settling behavior in charge-pump phase-locked loop design,¡± in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2009, pp. 469-472.

 

18. J. Qiao, X. Yu, W. Rhee, and Z. Wang, ¡°Customized zero-frequency control for hybrid FIR filtering in DS fractional-N PLL,¡± in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2009, pp. 2401-2404.

 

19. X. Yu, W. Rhee, Z. Wang, J. Lee, and C. Kim, ¡°A 0.4-1.6GHz low-OSR DS DLL with self-referenced multiphase generation,¡± in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2009, pp. 398-399.

 

20. L. Zhang, X. Yu, Y. Sun, W. Rhee, Z. Wang, H. Chen, and D. Wang, ¡°A hybrid spur compensation technique for finite-modulo fractional-N phase-locked loops,¡± in Proc. IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2008, pp. 417-420.

 

21. X. Yu, Y. Sun, W. Rhee, Z. Wang, H. Ahn, and B. Park, ¡°A DS fractional-N frequency synthesizer with customized noise shaping for WCDMA/HSDPA applications,¡± in IEEE Custom Integrated Circuits Conference (CICC), Feb. 2008, pp. 346-347. <AMD Student Scholarship Award>

 

22. X. Yu, Y. Sun, L. Zhang, W. Rhee, and Z. Wang, ¡°A 1GHz fractional-N PLL clock generator with low-OSR DS modulation and FIR-embedded noise filtering,¡± in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2008, pp. 346-347. <ISSCC Silkroad Award>

 

23. W. Rhee, et al., ¡°A uniform bandwidth PLL using a continuously tunable single-input dual-path LC VCO for 5Gb/s PCI Express Gen2 application,¡± in Proc. IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2007, pp. 63-66.

 

24. B. Chi, X. Yu, W. Rhee, and Z. Wang, ¡°A fractional-N PLL for digital clock generation with an FIR-embedded frequency divider,¡± in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2007, pp. 3051-3054.

 

25. Y. Liu, W. Rhee, D. Friedman, and D. Ham, ¡°All-digital dynamic self-detection & self-compensation of static phase offset in charge-pump PLLs,¡± in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2007, pp. 176-177.

 

26. B. Soltanian, H. Ainspan, W. Rhee, D. Friedman, and P. Kingnet, ¡°An ultra compact differentially tuned 6 GHz CMOS LC VCO with dynamic common-mode feedback,¡± in IEEE Custom Integrated Circuits Conf.(CICC), Sept. 2006, pp. 671-674.

 

27. M. Meghelli, et al, ¡°A 10Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90nm CMOS technology,¡± in IEEE International Solid-State Circuits Conference (ISSCC) Digest Tech. Papers, Feb. 2006, pp. 80-81.

 

28. K. Jenkins, W. Rhee, J. Liobe, and H. Ainspan, ¡°Experimental analysis of the effect of substrate noise on PLL performance,¡± in Digest of the 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), Jan. 2006, pp. 54-57.


29. M. Sorna, et al, ¡°A 6.4Gb/s CMOS SerDes core with feedforward and decision feedback equalization,¡± in IEEE International Solid-State Circuits Conference (ISSCC) Digest Tech. Papers, Feb. 2005, pp. 62-64.

 

30. W. Rhee, et al., ¡°A 10-Gb/s CMOS clock and data recovery circuits using a secondary delay-locked loop,¡±in Proc. IEEE Custom Integrated Circuits Conf.(CICC), Sept. 2003, pp. 81-84.

 

31. A. Molnar et al., ¡°A single-chip quad-band (850/900/1800/1900MHz) direct conversion GSM/GPRS RF transceiver with integrated VCOs and fractional-N synthesizer,¡± in IEEE International Solid-State Circuits Conference (ISSCC) Digest Tech. Papers, Feb. 2002, pp. 184-185.

     

    ¡ì Tutorials

    1. W. Rhee, ¡°Frequency synthesizers and PLL,¡± IEEE International Conference on Solid-State and Integrated-Circuit Technology (ICSICT) , Oct. 2008

    2. W. Rhee, ¡°Clocking frequencies and spectralizing clocks in SoC design,¡± IEEE International SoC Design Conference (ISOCC), Seoul , Korea , Oct. 2007

    3. W. Rhee, ¡°Practical design aspects in fractional- N frequency synthesis,¡± 12 th Workshop on Advances in Analog Circuit Design , Graz , Austria , Apr. 2003

    ¡ì Patents

      12 U.S. patents issued, 4 pending.


    ¡ì Ph.D. Thesis

      Multi-bit delta-sigma modulation technique for fractional-N frequency synthesizers , Ph.D. Thesis, University of Illinois , Urbana-Champaign , Aug. 2000.

     

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