Publication in 1999

1.  Semiconductor device and physics

SiGe microwave power heterojunction bipolar transistor

Zhang Jinshu, Jia Hongyong, Chen Peiyi

Chinese Jurnal of Electronics, Vol.8, No.3, 1999

We have developed a simple planar process compatible with Si process, and fabricated the SiGe heterojunction bipolar transistor (HBT) suitable for microwave power applications.  The current gain of the SiGe HBT is 50 - 320, the breakdown voltages of the collector junction and emitter junction are about 28 V and 5 V respectively. In common emitter configuration and class C operation, the SiGe HBT with continuous wave output power of 5 W and collector conversion efficiency of 63% and power gain of 7.4 dB has been obtained at the frequency of 900 MHz.

MEMS device for wireless communication Applications

Liu Zewen, Li Zhijian and Liu Litian

Electronics Science and Technology Review, No.7, 1999

Passive elements fabricated using MEMS technologies could be widely used in future wireless communication systems for their very low insertion loss, very small in size and compatibility with silicon IC process. Some important devices, such as micro-capacitance micro-inductor , micro-resonantor, micro-filter and micro-switches are reviewed and discussed in this paper.

Plasma dry etched p-Si micromold for permallog microstructure fabrication array

Z.W.Liu, L. T. Liu. Z. M. Tang, X. H. Wang and Z. J. Li

AEPSE'99, Beijing, China, 1999

In this paper we present a new process to fabricate permalloy (80%Ni and 20% Fe) Microstructures by plasma etching micromolds on p-type silicon and then electrochemically filling the micromolds obtained. Micromachined permalloy as a key soft magnetic material is widely used in MicroEletroMechanical Systems (MEMS) device fabrication. To obtain microstructures with 100 mm by 100mm lateral size, square trench is firstly drilled onto patterned wafer by plasma process. With CF₄ and SF₆ mixture as etchant gases, Trenches of 120um depth can be realized in 10 minutes. This process presents a relatively high etching rate to single crystal silicon. Trenches obtained are then served as micromolds for the following selective electrodeposition from trench base. To realize charge transfer between electrode and electrolyte, Boron dopants are selectively diffused to the trenches by hot process to form a thin layer of p doped silicon. A special clamp is designed to handle the wafer, which allows to apply a DC plating current from the wafer rear and to get a uniform metallic structure heights. High permeability (1700) Fe-Ni permalloy microstructures have been successfully obtained by the process.

Realization of a high performance dual axis accelerometer

Liu Zewen, Liu Litian Li Zhijian and Yi Futing

6^th National Annual Conference on Sensors and Transducer (STC'99), Oct. 19, 1999, Beijing

In this paper we present the study results on fabrication of a high performance dual axes accelerometer. The device is realized on silicon substrate with nickel as the structural materials. Main structures of the accelerometer are optimized with regards to its sensibility, damping characteristics, and so on.  The fabrication process includes two main steps: UV lithography on 10-mm-thick resist followed by a Cu electroplating for the sacrifice layer and deep X-ray lithography on 300-mm- thick PMMA resist followed by a Ni electroplating for the device structures.

Study on fabrication of a dual side alignment x-ray mask

Liu Zewen, Liu Litian, and Li Zhijian

10^th National annual conference on electron beam, ion beam and photon beam, Nov. 1999, Changsha

Deep X-ray lithography is a important method for high aspect-ratio MEMS structure fabrications. The technical difficulties appear in this process when a multi-exposure is required for the reason that most LIGA mask membrane is optically opaque. We resolve this problem by using a dual side alignment x-ray mask. In this paper, the study results of the fabrication process is presented. 

High-quality n-Si/i-p(+)-i SiGe/n-Si structure grown by ultra high vacuum chemical molecular epitaxy

Jinshu Zhang, Hongyong Jia

Journal of Materials Science:Materials in Electronics, Vol. 10, 1999

The n-Si/i-p(+)-i SiGe/n-Si structure was grown by ultra high vacuum chemical molecular epitaxy, and analysed by high resolution X-ray diffraction, cross-sectional transmission electron microscopy, and secondary ion mass spectroscopy. A high-quality SiGe base layer with an abrupt interface to the Si was obtained. No defects were observed in the n-Si/i-(+)-i SiGe/n-Si structure. Both the Ge and boron atoms are uniformly distributed in the p(+)-SiGe layer, and the changes of profile of both boron and Ge atoms are abrupt from the n-Si to the SiGe layer. A high-performance microwave power SiGe heterojunction bipolar transistor (HBT) was made from the n-Si/i-p(+)-i SiGe/n-Si structure. Therefore, device-quality n-Si/i-p(+)-i SiGe/n-Si structures can be grown by ultra high vacuum chemical molecular epitaxy.

n-Si/i-p-i SiGe/n-Si structure for SiGe microwave power heterojunction bipolar transistor grown by ultra-high-vacuum chemical molecular epitaxy

Zhang JS, Jin XJ, Jia HY, Chen PY, Tsien PH, Feng MX, Lin QY, Lo TC

Journal of Applied Physics, Vol. 86, No.3, 1999

The n-Si/i-p-i SiGe/n-Si structure, grown by ultra-high-vacuum chemical molecular epitaxy, was analyzed by cross-sectional transmission electron microscopy and secondary ion mass spectroscopy. It is shown that no defects are observed in the n-Si/i-p-i SiGe/n-Si structure, the interfaces between the SiGe layer and the n-Si layers are clear and planar, both the Ge and boron atoms are uniformly distributed in the p-SiGe, and the profiles of boron and Ge are abrupt from the n-Si to the SiGe layer. A high-performance microwave power SiGe heterojunction bipolar transistor was fabricated using the n-Si/i-p-i SiGe/n- Si structure. Therefore, ultra-high-vacuum chemical molecular epitaxy is one of the most promising methods for the growth of the Si/SiGe strained epilayers. (C) 1999 American Institute of Physics. [S0021-8979(99)04715-5].

Design and Manufacture of Novel Mesa Structure Wobbles Micromotor with Optical-Electronic IC

QI ChenJie , TAN ZhiMin , LIU LiTian , LI ZhiJian

Journal of Tsinghua Univ., Vol.39, No. Sl, 1999

This paper reports the development of a mesa flange bearing of a wobble micromotor with optical-electronic IC to increase the operation lifetime and expand a range of the velocity measured. The mesa flange bearing of the micromotor is made of single crystal silicon to replace for the polysilicon in the salient flange bearing micromotor. As a result, the mesa flange motor shows superior performance, such as higher strength, smaller frictional coefficient, and more difficult worn and solid in structure. The lifetime of the micromotor has been improved. A solid axle is used in the mesa flange bearing micromotor instead of a hollow-center axle in the salient flange micromotor, so that the deformation of axle from worn and force suffered are eliminated. Moreover, an optical-electrical IC for measuring rotative velocity of the micromotor is integrated in the micromotor, which can also be used as close loop control system or chopper light. Therefore, it is possible to manufacture the proper MEMS by this process, which is simple and compatible with IC process.

Optical-Diode Integrated on Micromotor for Velocity of Measurement

Qi Chenjie ,Hou yu, Liu Litian

STC'99, Beijing, China

A system of Measurement velocity is integrated on micromotor with Optical-diode in the paper. Under a rotor of micromotor , diodes are manufacturred and biased reverse. A laser light is illuminated on the diodes. The velocity of the micromotor is measured according to change of currents from a light current to a dark current. Then , the measurable range of velocity of the micromotor are expanded and the problem of a low measurable range in the video measurement system is solved. It has convenient in measurement , compatible in processes. It is possible to manufacture light-choppers and compose a MEMS.

Ferroelectrics-Silicon Microelectronic Integrated System (FSMIS)

Zhi-Jian Li, Li-Tian Liu and Tian-Ling Ren

Chinese Journal of Semiconducor，Vol.20, No. 3, 1999

Ferroelectrics-Silicon Microelectronic Integrated System (FSMIS) is the product of connection of ferroelctrics and silicon techniques. It has great meaning for the Microelectro-mechanical System (MEMS), memory and many other important fields. Here, several preparation methods of ferroelectric films on Si and some typical FSMIS applications are introduced, and the prospect of FSMIS in the future is reviewed.

Study on ferroelectrics-silicon integrated microphone and microspeaker

REN Tianling, LIU Litian, LI Zhijian

Journal of Tsinghua University, Vol. 39, No.S1, 1999

The aim of this paper is to lay foundation of the ferroelectrics-silicon integrated microphone and microspeaker. Considering the very excellent property of force-electric coupling of PZT, the design of cantilever form PZT ferroelectrics-silicon integrated microphone and microspeaker is proposed. The structure of PZT cantilever is designed using bimorph model, and then the technology flow is designed preliminarily. This ferroelectrics-silicon integrated microphone and microspeaker will be used in the  sound import of multimedia, mobile communication system and many other fields.

Memory of 21th Century–––– Silicon Based Ferroelectric Memory

Ren Tianling, Zhang Sheng, Liu Litian, Li Zhijian

Electronics Science and Technology Review, No.9, 1999

Ferroelectrics is used in silicon based ferroelectric memory. This new memory is an important use of ferroelectrics-silicon integrated system (FSMIS), it has high quality such as low operation voltage, low power, high density and good non-volatile property, and it will be an important kind of memory of 21th century.

Design of PZT Microphone and Microspeaker

Ren Tianling, Zhao Yang, Liu Litian, Li Zhijian

STC’99, beijing, Oct., 1999

In this paper, ferroelectrics-silicon microphone and microspeaker is proposed using PZT thin films. The core cantilever structure of PZT microphone and microspeaker is design using muiltimorph model. The theoretical design builds the foundation of the final realization of the integrated microphone and microspeaker.

Compensation introduced by defect complexes in p-type ZnSe

Tian-Ling Ren，Jia-Lin Zhu, Ziqiang Zhu and Takafumi Yao   

Journal of Applied Physics, Vol. 86, No. 3, 1999

Defect complexes in N-doped and As-doped ZnSe are studied by using discrete-variational local-density-functional (DV-LDF) method with cluster model. Based on the difference of formation energy between two complexes, it is found that N_Se-Zn-V_Se complex is a more efficient acceptor compensator than N_Se-Zn_int complex in N-doped ZnSe while As_Se-Zn_int  complex is a more efficient  acceptor compensator than As_Se-Zn-V_Se   complex in As-doped ZnSe. N_Se-Zn-N_Se complex with a 170 meV acceptor level and N_Se-N_Zn complex with a 88 meV donor level are respectively identified. A concept of  donor  states of  N molecules in ZnSe is confirmed.

Monolithic integration of HIP infrared detector with MOS readout switch

Wang Ruizhong, Chen Peiyi, Qian Peixin

Journal of Tsinghua University, Vol.39, No.S1, April，1999

In order to demonstrate the feasibility of fabricating monolithic integrated P⁺-Ge_x/Si_1-x/P-Si HIP infrared detectors with MOS readout circuit, the compatibility of P⁺-Ge_x/Si_1-x/P-Si heterojunction internal photoemission infrared detector (HIP IRD) with its CMOS readout circuit was analyzed and a feasible approach was presented. The experimental chip in which P⁺-Ge_x/Si_1-x/P-Si HIP IRD and its NMOS readout switch are monolithic integrated was fabricated with a 3 mm NMOS technology. The molecular beam epitaxy (MBE) grown detector without the dielectric cavity and antireflecting layer has a blackbody detectivity of 11 Mm.Hz^1/2.W ^-1 at a temperature of 77 K. The selective readout of the output signals of the detectors through the NMOS readout switch at 77 K has been achieved.

SIMS Analysis of the Cr-AlN Interface

Yue Ruifeng, Wang Youxiang, Chen Chunhua

Journal of Instrumental Analysis, Vol.18, No.3, 1999

A 200 nm Cr film was deposited on a polished AlN ceramic substrate at 200oC by electron beam evaporation. Depth profile was studied using MCs+-SIMS technique (detection of MCs+ secondary ion under Cs+ primary ion bombardment) after the samples were annealed in high vacuum. The variation of interface composition with annealing temperature and time is given. The results show that MCs+-SIMS technique is an effective method to analyze the interfacial diffusion and reaction between metal and ceramic.

SIMS study on the initial oxidation process of AlN ceramic substrate in the air

Ruifeng Yue, Yan Wang, Youxiang Wang, Chunhua Chen

Applied Surface Science, Vol.148, 1999

Secondary ion mass spectrometry (SIMS) and X-ray diffraction (XRD) measurement were employed to study the initial oxidation process of AlN ceramic substrate in the air at 850 ¾1100°C. The results show that there is already a very thin O-rich layer in the surface region of untreated AlN ceramic substrate. When the sample is annealed for 10 minutes, the O-rich layer becomes thicker rapidly with the increasing of annealing temperature. When it is annealed at 1100°C for 20 minutes, a continuous oxide layer is formed. In the end, combined with chemical thermodynamics, the initial oxidation mechanism near the surface of AlN substrate is discussed.

Studies of AIN and mullite ceramic substrates by SIMS and XRD

Yue Ruifeng, Wang Youxiang, Chen Chunhua

Bulletin of the Chinese Ceramic Society, 1999

The phases and surface compositions especially impurities of Dy₂O₃-CaO doped AlN and Cordierite-BaCO₃ doped mullite ceramic substrates for electronic packaging applications were investigated by secondary ion mass spectrometry (SIMS) and X-ray diffraction (XRD),  and an attempt to study the thermal oxidation problem of AlN surface by SIMS was  made.  The  results show  that there is a  contamination of  impurity elements such as Li, C, F, Na, K, Cl, Ti, Rb on AlN and  mullite ceramics surface with a different extent. There is an oxygen-rich layer on AlN ceramic surface, and it is broadened  obviously after annealing at  850^oC for 10 minutes in air.

Study on Interfacial Reaction of Ti/AlN by SIMS, RBS and XRD

Yue Ruifeng, Wang Yan, Wang Youxiang, Chen Chunhua

Surface and Interface Analysis, Vol.27, No.2, 1999

A 200 nm Ti film was deposited  on a polished AlN ceramic substrate at 200°C by electron beam evaporation and then annealed under high vacuum conditions. Secondary ion mass spectrometry (SIMS), Rutherford backscattering spectrometry (RBS) and X-ray diffraction (XRD) measurements were employed to probe the solid interface reaction between Ti and AlN from 200°C ¾ 850°C and the variation of interfacial composition distribution with annealing temperature and time was given. The ternary aluminides were discovered and the formation and developments of aluminides were observed in the interfacial region. The results indicate that the aluminides consist of Ti-Al binary and  Ti-Al-N ternary compounds. Finally the experimental results are explained with thermodynamics.

Study and design of Integrated pressure sensor with New Double Wheastone-bridge Configuration

Yue Ruifeng, Liu Litian, Li Zhijian

STC'99, Beijing, China, 1999

On the basis of studying the stress distribution in pressure sensor with silicon-cup structure  using finite-element method, two kinds of integrated pressure sensors with new double wheastone-bridge configuration are designed. The four piezoresistors consisting of each bridge  are placed in the same Region, and the compensation bridge is located in the diagonal of plastic diaphragm or in the region near plastic diaphragm  that the silicon thickness becomes thicker gradually. Because the compensation bridge is arranged near by the pressure sensitive bridge, which have the similar temperature characteristics, obvious reduction of the offset and its temperature drift is expected by the subtraction of the output of the two bridges. In addition, on-chip signal processing circuit is planed to be integrated in the bulk silicon region of the  pressure sensor using PMOS technology.

Fuzzy Neural Network and Its VLSI Implementation

CHEN Xi, JIN Dongming, LI Zhijian

The 11th national conference of IC&silicon materials of China, Dalian, China, 1999

This paper surveys the proposition and development of the fuzzy neural network and the related research works in VLSI. The fuzzy neural network is one of the promising solutions to overcome the drawbacks in either the fuzzy logic systems or the neural networks. Two approaches to modeling the fuzzy neural network are discussed, one is the neural network based fuzzy logic system, the other is the fuzzy neuron network. Because the VLSI implementation of the fuzzy neural network is relatively new issue, we summarize the VLSI implementation of fuzzy logic systems and the neural networks, then discuss the research works on the VLSI implementation of the fuzzy neural networks.

Design and fabrication of a practical fuzzy logic controller

Wang Chun, Jin Dongming

Journal of Tsinghua Univ., Vol.39, No. S1, 1999

A fuzzy logic controller is constructed to controller a metallic ball suspended in an electromagnetic field. The controller allows two premises, one conclusion, and nine rules. It explores a new method of fuzzification that subdues the information loss in the classification of accurate values. Modification of this method is also proposed. Simulation demonstrates that the fuzzy control method has superiority over the classic PID method, regarding the settling time, overshoot and stability. The controller is implemented by CMOS current-mode circuits and fabricated with improved CMOS technology. The test results of the chip show that the specifications of the task are principally achieved with a core area of 1.1mm² and a consumption of 10.7mW.

Design of a Programmable Fuzzy Logic Contorller

SHEN Jie，JIN Dongming，LI Zhijian

ACTAELECTRONICA SINICA, Vol.27, No.8, 1999

In this paper, we present a general-purpose programmable fuzzy logic controller implemented by analog hardware. The controller allowed two premises, one conclusion, and 81 control rules. It was constructed with current-mode multiple-valued CMOS devices which were fabricated in a 2-mm, 5V standard CMOS technology. All the fuzzy inference are processed in parallel, and the highest speed is l-mega times per second. With convenient I/O interface and reprogrammable rules, the PFLC can be applied in various areas.

Dual-MOSFETs Resistor

SHEN Jie，JIN Dongming，LI Zhijian

Journal of Tsinghua Univ., Vol.39, No.S1, 1999

This paper presents a method to implement resistor’s function by two MOSFETs which can be made through standard CMOS process. Both of the MOSFETs’ sources and drains are connected together and the sources are connected to the ground. One MOSFET works in saturate area while the other works in non-saturate area. The linearity error of the resistor is below 5%. The outpout voltage can vary from 1V to 4V. The value of the resistor can be adjusted easily ranging from 1kW to 100 kW. The fundamental theory and its application (e.g., in PFLC) are discussed, with the simulation and test results.

The development of Si_1-xGe_x material and bipolar devices

Jia Hongyong, Chen Peiyi, Sun Zimin

Semiconductor Information，Vol.36, No.3, 1999

Si_1-xGe_x material has many unique characteristics. The high performance strained epitaxial layer can introduce the concept of bandgap energy into the column IV devices. The epi-base Si_1-xGe_x heterojunction bipolar transistor (HBT) results in good performance. Because of the compatibility with Si process and the raoid progress of BiCMOS integration, the Si_1-xGe_x devices and process have already reach the industry application level. The development of Si1-xGex process and the improvement of the microwave circuits promote the development of microwave integrated circuits and the applicable frequency band of Si MMIC. The situation today implies that Si1-xGex technology have achieved the stage of extensive application in RF wireless telecommunication.

SiGe HBT technology: the new contender in the microwave and radio frequency application

Jia Hongyong, Chen Peiyi, Qian Peixin

Design of Integrated Circuits，No.8, 1999

This paper reviewed the development of Si_1-xGe_x material and its devices, showed its application in the microwave circuits. The good performance produced by the epitaxial Si_1-xGe_x base heterojunction bipolar transistor, and its compatibility with the Si process, greatly accelerated the performance of Si microwave integrated circuits, and improved the Si MMIC’s application frequency band. The situation today implies that Si_1-xGe_x technology have achieved the stage of extensive application in RF wireless telecommunication.

Study of the Si_1-xGe_x /Si epitaxy by ultra high vacuum chemical vapor deposition process

Jin Xiaojun, Jia Hongyong, Zhang Jinshu, Qian Wei, Han Yong, Liu Ronghua, Lin Huiwang, Chen Peiyi and Pei-Hsin Tsien

Journal of Tsinghua Univ., Vol.39, No.S1, 1999

An ultra high vacuum chemical vapor deposition system was designed and fabricated to grow strained Si1-xGex material for high performance device applications. The investigation of Si_1-xGe_x/Si hetero-epitaxy process was carried out on the laboratory made system. The rule about how the growth rate of Si_1-xGe_x and the fraction of germanium are varied with the flow of GeH₄ was researched. The experiment showed that the growth rate of Si_1-xGe_x increased distinctively with the flow of GeH₄ and the fraction of Ge in the epitaxial layer is about 2.5 times to the concentration of GeH₄ in gas phase. A simple reaction kinetic model was proposed to explain the relation between the fraction x and flow rate. The Raman spectroscopy analyses manifest that the epitaxial layer is completely strained. The diodes fabricated from this material showed nearly ideal performance.

Design and Fabrication of a novel silicon-based Micro-accelerometer

LI Junjun, LIU Litian and YANG Jinming

Journal of Tsinghua Univ. (Sci&Tech), Vol.39, No.S1, 1999

A novel resonant microaccelerometer is reported which is designed and fabricated using silicon micromachining technology. This microaccelerometer has a bulk silicon structure with supporting hinge and resonant microbeam fabricated at the same time. The resonant microbeam is driven by electric current and the frequency shift due to the change of acceleration is detected with a piezoresistive bridge. This accelerometer has the advantage of both the mature fabrication technology of piezoresistive type sensor and the quasidigital signal output of the resonant type sensor which make its output signal precise, stable and easily processed by digital circuit. The structure size varies from 3mm×4mm to 6mm×6mm. 

Quantum Mechanical Effects on Deep-Submicron MOSFET Subthreshold Characteristics

Ma Yutao, Liu Litian, Li Zhijian

Journal of Tsinghua Univ. (Sci&Tech), Vol.39, No.S1, 1999

Semi-classical and Quantum Mechanical carrier distribution models in subthreshold region are established and a new threshold voltage definition suitable for quantum mechanical theory is proposed through the solution of Schrodinger equation under triangular potential well approximation using Fermi Statistics . Carrier distribution and source drain current in subthreshold region are calculated in both semi-classical and quantum mechanical theories and the Quantum Mechanical Effects (QME) on deep-submicron MOSFET subthreshold characteristics are systematically studied for the first time. The results show that in highly doped substrate case, the carrier density and subthreshold current are lowered and threshold voltage is raised considerably due to QME, but the subthreshold swing factor(S) is entirely not influenced. This work indicates that QME on deep-submicron MOSFET subthreshold characteristics must be involved in modeling work and device design.

MOS Device Threshold Voltage Model Considering Quantum Mechanical Effect Including Multi-Subband Occupation

Ma Yutao, Liu Litian, Li Zhijian

Chinese Journal of Semiconductor, Vol. 20 No.3, 1999

With increasing of the substrate dopant concentration and decreasing of the gate oxide thickness，the influence of Quantum Mechanical Effects (QME) on deep-submicron MOSFET characteristics  are getting more and more significant。Experiments results show that QME can result in noticeable threshold voltage (Vth) shift。In this paper ,numerical solution with parabolic potential well and analytical solution with triangular well are compared ,and the validity of triangular well approximation is demonstrated。Based on the calculation of the subband structure in the quantized region in weak inversion regime ,the concepts of Quantum Effective State Density and Classical Effective State Density are proposed , the carrier distribution in subbands is analyzed and the two factors that influence the Vth shift are discussed。Finally, a quantum correction model to threshold voltage is given , which reveals the physical nature of the influence of QME on the Vth shift and gives consistent results with experiments.

A Discussion on the Universality of Inversion Layer Mobility in MOSFET’s

Ma Yutao, Liu Litian, Li Zhijian

IEEE Transactions on Electron Devices, Vol.146, No. 9, 1999

An obvious discrepancy exists in published research results [1-4] concerning the universality of MOS inversion layer electron mobility in nonuniform substrate doping profile cases. By thorough analysis of the data provided in [1] and the parameter extraction method used in [2], it is demonstrated that the discrepancy is simply due to the different definition of depletion layer charge in [1] and the invalid extraction of parameters from experimental data in [2]. Studies in this work show that inversion layer carrier mobility experiences the same universality feature in nonuniform doping substrates as in uniform ones.

The concept of Surface Layer Effective Density-of-States and it's Application in MOS structure modeling

Ma Yutao, Liu Litian, Li Zhijian

The 11th national conference of IC&silicon materials of China, Dalian, China, 1999

The concept of Surface Layer Effective Density-of-States (SLEDOS) is proposed based on the carrier distribution characteristics in MOS structure inversion layer. New charge distribution model both in semi-classical and quantum mechanical cases are developed based on SLEDOS. A high efficient method with robust stability is introduced in the model. Quantum Mechanical Effects (QMEs) on carrier sheet density and surface potential are studied in the present model. And then a new threshold voltage shift model due to QMEs is given.

Influence of QMEs on carrier concentration in MOS structure inversion layer under different temperature

Ma Yutao, Liu Litian, Li Zhijian

The 11th national conference of IC&silicon materials of China, Dalian, China, 1999

Low temperature devices are important due to the intrinsic high mobility and superior sub-threshold characteristics. Quantum Mechanical Effects (QMEs) have significant influences on carrier density in inversion layer and threshold voltage in MOSFET. In this paper, for the first time QMEs on carrier density in inversion layer of MOS structure under different temperatures are thoroughly studied. The carrier sheet density with respect to gate voltage in both semi-classical and quantum mechanical cases are calculated in a large range of temperature (77K~400K) and substrate doping levels (10¹⁶cm^-3~10¹⁸cm^-3). Results show that QMEs on carrier density substantially increase with the decrease of temperature. It is also shown that the superior sub-threshold characteristics can still remain even if the QMEs are considered. QMEs have larger influence on carrier density in weaker inversion region.

Comparison study of threshold voltage in modern MOSFET's

Ma Yutao, Liu Litian, Li Zhijian

The 11th national conference of IC&silicon materials of China, Dalian, China, 1999

Non-uniform substrate doping is a key structure in MOSFET to suppress the short channel effects. The doping profile has substantial influence on threshold voltage. The concepts of Strong Inversion threshold voltage and Constant Carrier Sheet Density threshold voltage are proposed for non-uniform doping devices. The equivalent of the two definitions are verified by numerical calculation. And then systematical comparison study on threshold voltage for devices with three typical structures (i.e. uniform doping substrate, step doping substrate and Gauss profile substrate) are carried out. Calculation results demonstrate the effects of step doping and other non-uniform doping structures on threshold voltage lowering. It is shown that for step doping structure, the depletion layer width is of no relation with the width of lower doping region provided that the latter is less that the former. An analytical threshold voltage model for step doping MOS devices is developed in this paper.

Study of A novel microflow control system

Pao Jiangtao, Liu Litian, Li Zhijian

STC'99, Beijing, China, 1999

A novel microflow control system is presented in this paper. The operation  principle, optimization of the structure design and the fabrication sequence for this system are also discussed. The processing and matericals used is fully compatible to the standard IC fabrication technology.

Study for the microflow control characteristics of micropump

Pao Jiangtao, Liu Litian, Li Zhijian

The 11th national conference of IC&silicon materials of China, Dalian, China, 1999

In order to control the pumping yield of the Al / Si bimetallic drivng micropump working in the msall microfloe region. the effects of  the freguency, duty cycle and amplitude of the driving signal on the flow are analyzed. It is shown that compared to the duty cycle and amplitude. the freguency adjustment is the best way to control the pumping yield, espeually for the tiny microflow. Ttis verfied by experiments.

Design and fabrication of a resonant microacce-lerometer

Li Junjun, Liu Litian, Yang Jinmin

STC'99, Beijing, China, 1999

The desing and fabrication of anovel resonant microaccelerometer were reported  in this paper. Its resonant microbeam is driven by electric current and the freguency shift due to the change of acceleration is detected with a piezorsistive bridge.The microaccelero-meter has a hinhly symmetric structure with its four corner supported .The performance of this resonant microaccelerometer is tested.

A novel structral piezoresistive silicon accelerometers

Li Junjun, Liu Litian, Yang Jinmin

The 11th national conference of IC&silicon materials of China, Dalian, China, 1999

The careful analysis is proceeded on sensing structures of the piezoresistive silicon accelerometers and the distribution of the stress concentration area is acguired to guide piezresi-stors location design of the Wheaston Bridge. A novel four-folded-hinge-support structre is presented has a high perfomance/area eatio. The chips of the piezoresistive type accelerometere are packaged tested . The result shows that this accelerometer has better performance.

Optimization and process compatibility of silicon integrated  micropump system

PANG jiangtao, LIU litian, LI zhijian

Journal of Tsinghua Univ., Vol.39, No.S1, 1999

The principle structure optimization,circuit design, fabrication Processing and preliminary experiments of a novel silicon integrated system are presented. This integrated system consists of two passive check microvalves, which are fabricated using bulk silicon micromachining techniques, and one bimetallic actuator with integrated microflow sensors and signal process circuits. The structure parameters are optimized and applied to design the actuator so that its performance is improved dramatically. The preliminary results show that the fabrication processing is very simple and fully compatible to standard IC fabrication technology. The dimension, maximum output pressure and maximum pumping yield of the system are        , 6mm×6mm×1mm，10 kPa and 44  respectively.

Research on sub-0.1mm gate-body-connected bulk MOSFET

LIU Weidong , LI Zhijian , LIU Litian

Journal of Tsinghua Univ., Vol.39, No.S1, 1999

High current driving capability and low standby power dissipation are now becoming an increasingly important subject in low-voltage CMOS transistor design.This paper proposed a Gate-body Connected (GBC) operation mode for bulk MOSFET at 0.5V power supply voltage to deal with this issue. Based on two-dimensional device numerical simulations, this work covers the research on device structure design, characteristics and physics in 0.5V GBC bulk MOSFET down to sub-0.1mm gate length. The major results obtained can be summarized as: first, 0.5V GBC operation features steep turn-off behave, high current drive, ideal logic voltage swings and negligible gate-to-body leakage currents; secondly, an Expoc structure which has shallow source/drain extensions and non-uniform vertical and lateral doping profiles shows excellent threshold voltage (V_th) rolloff down to 50 nm gate length and high immunity of V_th against channel doping fluctuations under the GBC mode of operation; and finally 0.5V GBC MOS transistors show comparable figure of merit in speed performance with 1V conventional counterpart in a wide V design space,. Furthermore, iit is found that the optimum gate oxide thickness for 0.5V sub-0.1mm GBC MOSFETs would be 3nm.

Study for the Quartz Resonator Force Sensor and Its engineering problems

Wang Xioahong, Zhu Huizhong, Dong Yonggui, Feng Guanping

Chinese Journal of Scientific Instrument, Vol. 20, No. 3, June 1999

This paper introduces a kind of quartz resonator force sensors with high precision. Several engineering problems are studied with methodology and experiments. The creep of the sensor of combinatory structure is resolved, and the effects of the thickness of resonator and its supporting on the stability of sensor are also analyzed.

Investigation on the Creep Characteristics of A Quartz Crystal Resonant Force Sensor

Xiaohong Wang^,, Huizhong Zhu, Guanping Feng

Measurement Science and Technology, Vol. 10, No. 12, Dec., 1999.

In this paper the creep behavior of a combinatory quartz resonant force sensor is discussed and the way to decrease it is analyzed. A viscoelastic model of the sensor considering the viscoelastic characteristics of the adhesive used to glue sensing element and other parts is introduced to analyze the creep behavior of the sensor. The result indicates that the features of adhesive can bring about remarkable effect on the creep behavior of the sensor. Among the feature parameters for the applied adhesive the glass transition temperature of the adhesive is the most important one. The adhesive must have a temperature of the glass transition much higher than its working temperature so as to reduce the creep error of sensors. These conclusions result in the design and development of a new adhesive, which can be used in wide temperature range.

Experimental Study for the Creep Characteristics of the Quartz Resonant Force Sensors

Xiaohong Wang, Yonggui Dong, Huizhong zhu, Guanping Feng

3^rd International Symposium on Test and Measurement, Xian, China, June, 1999.

This paper introduces a kind of quartz resonant force sensor of combinatory structure. Considering the problem of the creep which be found to be bigger than the other sensors of complicated structure, we have tacken experimental investigation in this paper to find the cause and the link of creep. It indicates that the features of adhesive can bring direct effect on the creep of sensors. The temperature of the glass transition becomes the most important feature index of the used adhesive. The adhesive must have a temperature of the glass transition much higher than its working temperature so as to reduce the creep error of sensors. These conclusions result in the design and development of a new adhesive which can be used in wide temperature range.

Power Characteristics of SiGe Heterojunction Bipolar Transistor at 900MHz

Zhang Jinshu, Jin Xiaojun, Jia Hongyong, Chen Peiyi, Tsien Pei-Hsin ,Lo Tai-Chin, Yang Zengmin, Huang Jie, Liang Chunguang

Chinese Journal of Semiconductor, Vol. 20, No. 4, 1999

The microwave power performance of the SiGe heterojunction bipolar transistor fabricated by quqasi-washed-emitter-base process, is investigated. The cutoff frequency of the SiGe HBT is 7.5GHz at collector-emitter voltage Vce of 4V and collector current Ic of 300mA. In common emitter configuration and class C operation, the SiGe heterojunction bipolar transistor with continuous wave output power of 5W and conversion efficiency of 63% and power gain of 7.4dB is obtained at frequency of 900MHz.

Emitter-Ballasting-Resistor-Free SiGe Microwave Power Heterojunction Bipolar Transistor

Jinshu Zhang, Hongyong Jia, Pei-hsin Tsien, and Tai-Chin Lo

IEEE Electron Device Letters, 20-7, 1999

The emitter ballasting resistor is used to equalize the current distribution between the emitter stripes in power transistor, but it will degrade the output power, power gain, and power added efficiency. Experimental result indicates that the current gain of uniform-base  SiGe heterojunction bipolar transistors  (HBT’s) decreases with the increase of the temperature above temperature of 160 ,so the current distribution is equalized by itself to some extent. Therefore,  the microwave power SiGe HBT’s without emitter ballasing resistor were fabricated for the first time, and the continuous output power of 5 W and power added efficiency of 63% were obtained under Class C operation at frequency of 900 MHz. Hence, the emitter current density of the SiGe HBT’s with emitter width of 6 mm is 0.79 A/cm.

High-quality n-Si/i-p⁺-i SiGe/n-Si structure grown by ultra high vacuum chemical molecular epitaxy

Jinshu Zhang, Hongyong Jia, Peiyi Chen, Pei-hsin Tsien, F. X. Feng, Q. Y. Lin, Tai-chin Lo

Journal of Materials Science:Materials in Electronics 10, 1999

The n-Si/i-p⁺-i SiGe/n-Si structure was grown by ultra high vacuum chemical molecular epitaxy, and analyzed by high resolution X-ray diffraction, cross-sectional transmission electron microscopy, and secondary ion mass spectroscopy. A high-quality SiGe base layer with and abrupt interface to the Si was obtained. No defects were observed in the n-Si/i-p⁺-i SiGe/n-Si structure. Both the Ge and boron atoms are uniformly distributed in the p⁺-SiGe layer, and the changes of profile of both boron and Ge atoms are abrupt from the n-Si to the SiGe layer. A high-performance microwave power SiGe heterojunction bipolar transistor (HBT) was made from the n-Si/i-p⁺-i SiGe/n-Si structure. Therefore, device-quality n-Si/i-p⁺-i SiGe/n-Si structures can be grown by ultra high vacuum chemical molecular epitaxy.

Summary of Research on SiGe Devices

Sun Zimin, Dong Zhiwei

Semiconductor Information，Vol.36, No.1, 1999

This paper describes the main research directions of SiGe devices and the current state of the researches in SiGe materials and SiGe devices. The future development of SiGe devices is also compares with that of Si Devices and GaAs devices.

Performance of submicron And deep-submicron Conventional/LDD MOSFET

SUN Zimin,LIU Litian, LI Zhijian

Journal of Tsinghua Univ., Vol.39, No.S1, 1999

Conventional and LDD structured NMOSFET  were fabricated. Results of simulation and practical measurement indicated that, if the device structure is appropriately designed to limit the value of I_off in a acceptable range, MOSFET working in a carefully defined and relatively lowered voltage region will have better performance and smaller hot carrier effect than those of LDD MOSFET with same channel length. Meanwhile, one can get the advantage of the conventional Structure with less area and reduced working power dissipation. It was shown that the conclusion is True even for MOSFET with channel length of 0.5mm and 0.35mm, which are now in mass production Using LDD structure.

A quisa-liga process using multilayer photo-resist technology

Sun Zimin, Liu Litian, Li Zhijian

Microfabrication Technology, No.2, 1999

LIGA technology play a very important role in the fabrication of MEMS.A new quisa-LIGA process using multilayer photoresist technology is presented in this paper. It can transfer the patterns onto the much thicker photoresist layer by common photo-lithography machine and large aspect ratio can be obtained.

Research on electrostatic comb-drive structures

WU Hui, LIU Litian , YANG Jingming

Journal of Tsinghua Univ., Vol.39, No.S1, 1999

Electrostatic comb-drive structure (ECS) have become the integral components of many important micromechanical devices, such as resonators ,accelerometers, gyroscopes and vibromotors , in which ECS act as actuators ,sensors or both .This paper focused on the design and fabrication of ECS with polysilicon surface micromachining technology. The theoretical analysis and computer simulation of ECS were performed. Several key steps in the surface micromachining process were essential to the successful realization of ECS, and were investigated too . The longest free-standing cantilever reached over 200mm ,and ECS were successful released. Output signals, which changed with DC bias ,AC drive voltage and frequency, indicated that ECS did vibrate.

2.Integrated Circuit

New generation speech CODEC for digital telephone switching

WU Xingjun, WEI Shaojun

Journal of Tsinghua Univ., Vol.39, No.S1, 1999

In order to decrease cost and improve performance of Digital Telephone Switching, a four-channel CODEC device based on DSP was designed. In this device, oversampled analog to digital converting technique and digital signal processing technique were used. Due to these techniques, it is possible to take the advantages of digital VLSI technique, implement multi-channel speech CODEC in a single chip, and make the cost of switching low. Meanwhile, programmable digital filters were used, the performance of the system can be improved just by adjusting the coefficients of the filters by software according to different line characteristics. This device was fabricated in a 0.5um CMOS process with double poly and 3 layers metal, and integrated on a die size of 25 mm². Measurements show that all the necessary CCITT’s recommendations are fulfilled.

An Embedded Dual-port High Speed SRAM Compiler Design

Deng Haifei, Gao Zhiqiang

The 11th national conference of IC&silicon materials of China, Dalian, China, 1999

With the development of submicron technology, more and more designers deploy cores in the design of complicated system. Core library plays an important role in the system design. In order to keep step with the new trend of IC design, an instance of core library design, an embedded dual-port high speed SRAM compiler, is described here. It can generate the netlist, VHDL model, Verilog model and layout of SRAM according to the parameters provided by customers. Some key issues such as design flow, circuit and layout design are elaborated here. It will redound to the design of other core libraries such as datapath, ROM and multiplexer compiler etc.

VLSI Implementation of an Encryption Algorithm for ICCards

LI Zhi-min; GE Yuan-qing; LIANG Song-hai

Microelectronics, Vol.29, No.6, 1999

It is an important method to encrypt the transferring data for improving the security of IC cards. VLSI implementation of an encryption algorithm utilzed in IC cards is investigated in the paper. Design and verification of the algorithm are carried out by using Hardware Description Language(VHDL).The gate-level simulation demonstrates the correctness of the design.

A multi-band UV decision method

Yiting Zhu , Yongming Li ,Hongyi Chen

Microelectronics&Computer, Vol.16, No.5, 1999

This paper gives a method of UV decision, considering the frequency waveform of each sub-band of LPC residue, autocorrelation function is calculated, and its periodicity and non-periodicity are analyzed obtain decision of voice or unvoice, which can greatly decrease the computation complexity and reduce the memory required in the MBE-LPC Algorithm. The method is in coincidence with that of full-band speech Uvdecision. The subject listening test shows that the speech synthesized by this method is not inferior to that by the standard MBE algorithm..

Programmable wavelet packet transform processro

Xiaodong Wu, Yongming Li, Hongyi Chen

Electronics Letters Vol.35, No.6, 1999

Programmable one-dimensional discret wavelet packet transform processor is presented. Compared with existing architectures, the proposed processor can carry out both wavelet transfoms and wavelet packet transfoms, and is suitable of high-tap filters and high decomposition levels. It is small, and is especially suitable for on-chip or sinle-chip implementation.

CMOS Voltage-Controlled Oscillatro for PLL Freequency Synthesis

Chunhui Zhang and Yongming Li

ISSPIS’99, Guangzhou, China, 1999

This paper describes two Voltage-Controlled Oscillator circuits simulated in a 0.6-um CMOS technology by TSMCompany, a simple oscillator and a differential one. The former VCO exhibits a maximum frequency more than 2-GHz and 7.5mW power consumption (5V). The limitation of the maximum VCO frequency in specific technology is also discussed.

Design of a 1.8kbps MBE-LPC Vocoder

Yongming Li , Hongyi Chen, Yithin Zhu

ISSPIS’99, Guangzhou, China, 1999

The paper presents a 1.8kbps MBE-LPC vocoder which combines MBE model with LPC model. Using LPC characteristic parameters to represent spectrum of speech frame, analysis of LPC residue abstracts pith and multiband U/V decision. Using MBE model to obtain synthesised speech. The quality is better than LPC-10e. The vocoder needs smaller storage memory and simplifies compuation. It is implemented in DSP.

A multi-band Uvdecision method based on LPC analysis

Yongming Li Hongyi Chen, Yiting zhu

ISSPIS’99, Guangzhou, China, 1999

This paper gives a simple method of UV decision on sub-bands, which can greatly decrease the computation complexity and reduce the memory required in the MBE-LPC algorithm and decrease the difficulty in DSP  real-time fixed-point implementation and integrated circuits chip Considering the  frequency waveform of each sub-band of the LPC residue, the autocorrelation function is calculated, and its periodicity and non-periodicity are analyzed, to obtain decision of voice/unvoice, the principle of this kind of UV decision is in coincidence with that of full-band speech UV decision. The subjective listening test shows that the speech synthesized by this method is not inferior to that by the standard MBE algorithm.

VLSI Architecture for 1-D Discrete Wavelet/Wavelet Packet Transform

Wu Xiaodong, LiYongming, Chen Hongyi

Chinese Journal of Semiconductor, Vol.20, No.3, 1999

Being a powerful signal processing tool, the wavelet/wavelet packet transform is being used in more and more research areas. Therefore its hardware implementation is being paid more attention to. Inthis paper, based on its use in speech chding ,a VLSI architecture for 1-D discrete wavelet/wavelet packet transform is pesented. Unlike the existed solutions, this architecture can be used for wavelets with different support length, for data segments with different length, and for different decomposition level. It has the features of flexibility and programmability, and is suitable to be implemented as a on-chip transform unit for many systems, and can also be implemented as a single chip.

VLSI programmable wavelet packet transform processor

WU Xiaodong, Li Yongming, CHEN Hongyi

Journal of Tsinghua University, Vol.39, No.S1, 1999

This paper investigates the hardware implementation of wavelet packet transforms. Because the existed hardware implementation schemes are often limited in application by being unsuitable for long support length wavelets and high level decomposition, this paper gives a hardware implementation scheme based on a two-buffer-structure which is programmable and universal. A universal wavelet packet transform chip is designed according to the scheme, and it is suitable for single chip implementation of being used as an engine unit in ,amuy application systems. The chip is simulated on FPGA with an ALTERA’s FLEX10K chip by using SYNOPSYS’ FPGA-COMPILER and ALTERA’s MAX+PLUSII.

One type of switched-current ΣΔ modulator

XU Gang, SHEN Yanzhao

Journal of Tsinghua University, Vol.39, No.S1, 1999

Switched-current circuits (SI)broought about a new trend in the field of analog-signal process. To explore more thoroughly and extensively on this technique, a novel two step SI circuit (S²I) is introduced, and several methods to minimize the clock-feedthrough effect are analyzed. A balanced  S²I integratro is designed in favor of this circuit. Then on the basis fo integrators, a differential balanced second orderΣΔ modulaator is devised, whose fabrication process is absolutely compatible with the standard CMOS digital technique. With the HSPICE parameters of 1.2um digital CMOStechnique,  the circuit was simulated, and the results was verified and evaluated by the programs of MATLAB as well. From this results, the function of the  ΣΔ modulator is validated.

Design of A Voice-Band MOSFET-C Continuous-Time Lowpass Filter

Li Wei-guo and Shen Yan-zhao

Microelectronics, No.1, 1999

A fuly integrated voice-band continuous-time MOSFET-C filter is described, which was designed based on the technique fo fully balanced networks and was fabricated in a 2um CMOS N-Well polysilicon Technology.The filter implements a fifth order chebyshev low-pass transfer function with 0.1-dB passband ripple and 3.4kHz cutoff frequency. It’s internal operational amplifier use a fully differential operational amplifier with accurate output balancing. And the experiment results are discussed.

Design of Neural Network/Fuzzy Logic Recognizer for Handwritten Digit Recognition

Li Guoxing and Shi Bingxue

Journal of Tsinghua University, Vol.39, No.S1, 1999

A compact current mode VLSI neural network/fuzzy logic recognizer for unconstrained handwritten digit recognition is put forward in this paper based on neural network and fuzzy logic recognizing algorithms. This processor can not only realize single or multi layer perception, but also function fuzzy logic algorithm for recognition. It also has the advantages of weight programmability, structure reconfigurability, input feature vector variability, self-adaptability and inter-chip expandability. The processor mainly consists of programmable neural processing units(NPU), fully differential switched-current integrators and nonlinear transfer units.  NPU is the core of this recognizer whose weights can be refreshed by the latches. It can output current from –7I­_ref to +7I_ref or from 0 to 15I_ref according to different configuration, where I_ref is a small reference current. The integrator can accumulate these currents and provide the final current to nonlinear transfer unit. The transfer unit gives the final binary recognizing results. This recognizer just needs about ten thousand transistors and is compatible with standard digital CMOS technology.

A Membership Programmable Fuzzy Recognizer

Gu Lin and Bingxue Shi

Journal of Tsinghua University, Vol.39, No.S1, 1999

A membership programmable fuzzy recognizer is proposed. The processor employs the “Sum-Sorting” fuzzy operation in order to improVe the performance of recognition. In the processor, membership funCTion can be programmable to meet the requirements of different fields. The core circuits in the fuzzy integrated circuit has been successfully manufaCTured in 2mm N-well standard digital CMOS process. Experimental results show these circuits haVe good performance .

Realization of Pulse-Width Modulation Chip for High-efficientcy High-precision Switching Regulator

Chen Lu, Shi Bingxue, Dai Tiejun, Li Guoxing, and Lu Chun

Journal of Tsinghua University, Vol.39, No.S1, 1999

The realization of pulse-width modulation chip for switching regulator is analyzed. An architecture of pulse-width modulation chip is proposed，which is suitable for high-current, high-efficiency, high-precision and programmable switching regulator on PC mainboard. This chip integrates the control, output adjustment, monitoring and protection function of switching regulator. Its characteristics also include fast transient response, small turn-on overshoot, small output voltage fluctuations with output current changes. Major circuits in this chip and the whole DC-DC converter system are simulated by HSPICE. The chip is fabricated with 1.7mm BiCMOS process, a switching regulator system based on this chip for Pentium serial PC mainboard is set up. At last, the performance of this system is tested, and the result conforms to Intel VRM8.1 standard.

Two Modified Current-Mode WTA circuits

Li Guoxing and Shi Bingxue

ACTA ELECTRONICA SINICA，Vol. 27, No. 11, 1999

A current mode novel multifunctional WTA network with smart structure is put forward in this paper. This network is reconfigurable with a high precision. It can also realize both absolute rejecting function and relative rejecting function. The weighted sum of all the input currents is regarded as a relative threshold in the first kind of relative rejecting when this network is configured in 2-WTA and so it has some adaptibility. If the difference between the first maximum and the second maximum input currents is less than a given value or a ratio of the first maximum input current, then a relative rejecting signal is given by the second kind of network. In this case, the network is usually used as a general 1-WTA. These two kinds of rejecting play an important role in the field of pattern recognition. HSPICE simulation of this network gives a good performance.

Design of A VLSI Implementation Oriented Off-line Handwritten Digit Classification System

Li Guoxing and Shi Bingxue

ACTA ELECTRONICA SINICA，Vol. 27, No. 11, 1999

A VLSI implementation oriented off-line handwritten digit classification system based on cellular neural network and two layer perceptron is presented in this paper. The cellular neural network is used to extract the connected component feature of normalized 20X20 handwritten digit image. These features are fed into the two-layer perceptron after proper compression in time-sharing mode. The two layer perceptron has a structure of 80X20X10 with local connection and it mainly consists of a weight programmable NPU array, switched current integrator and current comparators. This classification system has a smart structure and it can be directly mapped into current circuits whose technology is compatible with standard digital CMOS VLSI.

A Programmable and Expandable Current-mode Hamming Neural Network

Lin Gu and Shi Bingxue

Chinese Journal of Electronics, Vol.8, No.3, 1999

A programmable and expandable current-mode Hamming neural network is proposed in this paper, which is amenable to many pattern recognition applications. In the Hamming network , the calculating circuit for template matching is composed of current mirrors. A current-mode sorting circuit sorts the matching scores in order to select the exemplar patterns that most and more resemble the input unknown pattern, instead of employing MAX operation to only select the exemplar pattern that most resembles the input pattern. Sorting operation greatly improves the performances of the Hamming network and makes the network especially advantageous used in multi-stage cascade system. In the Hamming network, the exemplar patterns are programmable to meet different applications. In addition, the network circuit chips can be easily expanded by interconnecting multiple chips so that its flexibility is greatly improved. At present, the core circuit in the Hamming network has been successfully manufactured in 2mm N-well standard digital CMOS process. Measured experimental results are given to illustrate the performances.

A Current-mode CNN Feature Extractor for Handwritten Digit Classification

Li Guoxing and Shi Bingxue

CCNNSP’ 1999, Shantou, China, Dec. 1999

A current-mode CMOS feature extractor based on cellular neural network is put forward and implemented in this paper. This feature extractor can extract connected component feature from normalized handwritten digit binary image in horizontal, vertical and two diagonal directions for handwritten digit recognition, and finally an 80 bit binary feature vector can be obtained after proper compression.

An Expansible Current-mode Sorter for Pattern Recognition

Gu Lin, Bingxue Shi

International Joint Conference on Neural Networks (IJCNN’99), Washington, USA, July, 1999

An expansible current-mode sorter for pattern recognition is proposed. Its structure is simple and chips can be easily used in expansible way. At present, the sorting circuit has been successfully fabricated in standard N-well digital CMOS process. Experimental results show that the sorting circuit has good performances.

A Current-Mode Programmable and Expandable Hamming Neural Network

Guoxing Li and Bingxue Shi

International Joint Conference on Neural Networks (IJCNN’99), Washington, USA, July, 1999

A current-mode programmable and expandable Hamming neural network with the ability to output the first K maximum matching currents from M ones in sorting order is put forward in this paper. The binary template can be programmable or learnable if needed in this network and the K maximum matching currents can be output in sorting order based on the switched-current technique, and its corresponding labels are also output in time sharing mode in the same time. The complexity of this network is just O(N) and its scale can be easily expanded. This network has been fabricated in a 1.2mm CMOS technology. Both Hspice simulation and experimental results of the prototype chip show good performance.

A Current-mode Fuzzy Processor For Pattern Recognition

Gu Lin and Bingxue Shi

Journal of Circuits and Systems, Vol.4, No.3,1999

A current-mode fuzzy processor for pattern recognition is proposed. The “weighted sum” synthetic function is employed, and its weights are able to be adjusted to improve adaptability of this system. The proposed fuzzy processor is able to output synthetic membership and corresponding standard patterns according to magnitude of membership. This will greatly improve the performance of the hardware system, especially for multi-stage cascaded system. The fuzzy processor has been successfully fabricated in single-metal single-poly 2mm N-well standard digital CMOS process. Experiment results show the processor chip has good performance.

A Novel Current Mode Sorter with High Resolution

Li Guoxing and Shi Bingxue

Chinese Journal of Semiconductors, Vol. 20, No. 8, 1999

A novel current mode sorter circuit with compact structure and high resolution is put forward in this paper. This sorter has a simple structure with the complexity of O(N) and a large dynamic range. It also needs less clocks and biasing signals. This sorter mainly consists of WTA circuit, trigger circuit and switched current track/hold circuit. Its resolution is within the range of one percent, dependent on the resolution of WTA and switched current track/hold circuits. This circuit can be implemented in standard digital CMOS technology.

A Improved Current-mode Sorter Based on Magnitude

Gu Lin, Bingxue Shi

Chinese Journal of Semiconductors, Vol. 20, No. 7, 1999

A improved current-mode sorter based on magnitude is proposed. This sorter has good function of sorting. The structure of this sorter is simple and flexible. It was successfully fabricated in 2mm N-well standard digital CMOS process. Experiment results show the sorter has high precision and resolution. It could be widely used in a lot of fields and has high application value.

Computational Intelligence: What is “the great challenge?”

Shi Bingxue

International Academic Developments, No.3, 1999

Computational Intelligence is currently the leading-edge field of the world, which includes three branches: neural networks, fuzzy logic and evolutional computation. In recent years, it has got great advances and also suffered some difficulties. The new progresses presented on world Conference on Computational Intelligence (WCCI’98) are introduced in the paper. The great challenge for computational intelligence and the focus, difficult topics and opportunities for current research work are discussed. The main topics of each branch and trend of joint research between branches are described. Finally, some advances in hardware implementation for increasing speed and real-time processing are introduced.

A Novel Extensible Current-mode Sorter Based on Magnitude

Gu Lin, Bingxue Shi

ACTA ELECTRONICA SINICA，Vol.27, No.5, 1999

A novel extensible current-mode sorter based on magnitude is proposed. This sorter not only outputs sorted currents based on magnitude, but also determines the order of input terminals corresponding to the order of input currents magnitude.The time and area complexity of the sorter is O(N).The structure of this sorter is simple, flexible and its scale can be easily extended.Ihis sorter is able to be directly fabricated in a standard digital CMOS process and easily implemented in VLSI technology.

A Multi-input Current-mode Fuzzy Integrated Circuit For Pattern Recognition

Gu Lin, Bingxue Shi

IPMM’99, Hawaii, USA, July, 1999

A multi-input current-mode fuzzy recognition integrated circuit is proposed in this paper,which is amenable to many pattern recognition applications. It can accept multiple inputs that represent multiple features of an unknown pattern in time-shared way.The principle of the fuzzy circuit is based on “Sum - Sorting” rule. In the fuzzy circuit, membership function generators employs current-mode circuit to generate memberships corresponding to each standard pattern according to the input features. Switched-current accumulators are adopted to realize the Sum function to get synthetic memberships.Sorting circuit sorts all of synthetic memberships based on their magnitudes , and finally recognition results are outputted. The fuzzy integrated circuit has been successfully manufactured in 2mm N-well standard digital CMOS process. It has been applied to speaker-independent Chinese digits speech recognition with the high recognition speed of 1.7´10⁵ digits per second and the high recognition rate( the first recognition rate is more than 90% , the second recognition rate is more than 98% ).

A Current-mode Sorting Circuitfor Pattern Recognition

Gu Lin, Bingxue Shi

IPMM’99, Hawaii, USA, July, 1999

A current-mode sorting circuit based on magnitude for pattern recognition is proposed. In this sorting circuit, symmetric WTA (Winner Take All) network is employed to find maximum current. Then, sorted currents based on magnitude are outputted in time-shared way. This sorting circuit has a simple and flexible structure. Results of experiment show that it has good performances. It can be widely used in pattern recognition, classification, expert system and so on.

A Reconfigurable Current Mode K-WTA Circuit with O(N) Complexity

Li Guoxing and Shi Bingxue

Chinese Journal of Electronics, Vol. 8, No. 3, 1999

A novel current mode k-WTA network is proposed in this paper. This WTA network has a simple structure with O(n) complexity and high resolution , it is also reconfigurable and easy-expanding. Both HSPICE simulation and test chip with six ports fabricated in 2mm standard CMOS technology give good results.

A Novel Fuzzy Processor Based on Second Generation Switched-Current technology for Pattern Recognition

Gu Lin, Bingxue Shi

<Selected Works of Fuzzy Technolgy and Neural Technogy>, Publishing House of Beijing Aeronautics and Aerospace University, Oct. 1999

A novel fuzzy processor based on second generation switched-current (SI) technology for pattern recognition is proposed. It accepts multiple inputs that represent multiple features of an unknown pattern in time-shared way. Membership function generators generate memberships corresponding to each standard pattern according to the input features, then different weights are used for different feature memberships. Then accumulators accumulate multiple weighted memberships to get synthetic memberships. Finally, MAX circuit finds the maximum synthetic membership and the recognition result are obtained. The proposed processor is current-mode. The accumulator is composed of second generation SI circuits, so the resolution of system is good. In order to improve adaptability of this system and extend its application field, weights of synthetic function are able to be adjusted. The results of PSPICE simulation show this system has good performance and high resolution. On the other hand, its scale is easily to be extended. Since the switched-current technology is employed, this system is fully compatible with a standard digital CMOS technology, and is easily to be integrated in mixed analog-digital system and implemented in VLSI.

A Novel Switched-Current Fuzzy Processor For Pattern Recognition

Gu Lin and Bingxue Shi

<Selected Works of Fuzzy Technolgy and Neural Technogy>,Publishing House of Beijing Aeronautics and Aerospace University, Oct. 1999

A novel switched-current fuzzy processor for pattern recognition is firstly proposed. The proposed fuzzy processor is not only able to find the stand pattern with the largest level of matching, but also output levels of matching and stand patterns corresponding to these levels according to magnitude of levels. On the other hand, this network could realize the absolute rejection and the relative rejection. This improves the reliability of the system. The structure of this processor is simple, flexible and its scale can be easily extended. PSPICE simulation shows that the processor has high resolution and high precision. Since switched-current structure is employed, this processor is able to be fully compatible with a standard digital CMOS process and easily implemented in VLSI technology.

System level fault simulation algorithm and system SysFsim for VLSI of system on a chip circuits

Sun Yihe, Xu Lei, Ma Yuhai, Chen Hongyi

Journal of Tsinghua University, Vol.39, No.S1, 1999

A novel system level fault algorithm and simulation environment for VLSI of system on a chip circuits has been presented. It is SysFsim, which consists of two system level fault simulators: Hsim and Bsim. The system level is the upper level composed of both combinational modules and sequential modules, and the gate level is the lower representing the gate level structure for only the module under simulation (MUS). To fault simulate a part of a circuit system at the gate level, the rest of the system is not required to be described at the gate level. A gate level fault simulator is applied to the faults in the MUS. At the system level, behavioral or function simulation techniques are applied to simulate, evaluate and propagate all the possible high level fault effects. The experiments have been done. It is proved that a performance of SysFsim is better than other ones. The fault coverage simulated benchmark circuits by Hsim and Bsim is 94.3%, 95.0%, respectively. After insertingTH_TE100 PLA/ROM testing generation, it is able to simulate PLA/ROM that contains the array 100 in by 100 out.

VLSI path delay fault testing method based on Electron beam probe technology

Wu Qifa, Sun Yihe

Electronic Testing (Supplement), 1999

In this paper, a path delay fault testing method based on Electron beam probe technology is presented. First the working principle of EB-P and the results of some experiments are put forward, which explain that using EB-P to measure path delay is trustable. Then the method is presented which use EB-P as test point. As a kind of test point that only adds observability, EB-P has the merit of reducing the number of path delay faults that need to be tested directly and the merit of rendering untestable path testable. Furthermore this method don’t overhead circuit area, and don’t increasing the delays of all the paths that go through the test point. It also needn’t several clock periods. We illustrate this by some examples.

Pitch synchronous speech analysis method

Yang Huimin, Chen Hongyi, Sun Yihe

Journal of Tsinghua University, Vol.39, No.S1, 1999

A new speech analysis method based on pitch period is presented in the paper. The pitch contour, i.e., the time-varying pitch period, is first estimated from the speech signal. Then the speech signal is time warped according to this pitch contour, where the original signal with time-varying pitch period is converted to a signal of constant pitch period. Time invariant transforms, such as modulated lapped transform, etc. can then be performed on the signal of constant pitch period. Since those transforms are pitch synchronous, the outputs of the transforms represent the subband signals of the speech and are of clear physical meaning, which facilitates the subsequent quantization and coding. Therefore, the analysis method can be used in low bit rate speech coding allowing higher compression ratio or improved reconstructed speech at the same bit rate.

Strategies for Top-Down Design of a High Frequency Large Scale ASIC

Sun Yihe and Qiu Xiaohai

Microelectronics, Vol. 29, No. 4, 1999

Problems encountered in the course of designing a very large scale and high frequency ASIC are dealt with. It is found that it is not easy to apply constraints during synthesizing, due to the form of hardware description language. Also, for high fan-out signals, the interconnection delay is large because of the very large scale of the circuit. Strategies for solving these problems are presented.

Graph-Based resource allocation algorithm for Testability

Li Li，Shaojun Wei，Zhilian Yang

Journal of Tsinghua University, Vol.39, No.S1, 1999

Testability synthesis refers to the synthesis process considering testability, which aims at making the generated circuit contain testable structure. Early testability synthesis is mostly related to logic synthesis. This paper presents a novel testable resource allocation algorithm, which is based on an operator compatibility graph out of which the testability information is integrated. A partitioning process will divide the operator compatibility graph into equivalent sub-classes and operators in a sub-class will share the same resource. According to the algorithm proposed, a high-level synthesis for testability system (Testsyn) has been built. The experiments show that the circuit structures unable or difficult to be tested can be avoided.

Using Branch-Bound Left/Right Edge Searching Algorithm for Testable Rgister Binding

Li Li，Shaojun Wei，Zhilian Yang

Proceedings of The 11th national conference of Semiconductor Integrated Circuits and silicon materials, Dalian, China, 1999

According to the three rules directing high-level testability synthesis, this paper proposes a testable register assignment algorithm based on left and right branch-and-bound searching. The algorithm uses left and right branch-and-bound algorithm to assign the variables in scheduled control-flow data graph to corresponding registers. In order to enhance the testability of the design, we consider the three rules when defining the sharing prefer function between variables. Some examples are given to show the efficiency of the algorithm.

Introduction of the development of high level design methodology for Deep Sub-Micron VLSI

Lu Ruibing and Wei Shaojun

Electronic Science&Technology Review, 1999

As the feature size of VLSI circuit scales down, signal delay introduced by wire becomes the key factor dominating circuit’s performance. Ignoring wire delay, traditional high level design methodology meet great challenge. How to minimize the impact of the wire delay becomes one of the most important subjects in VLSI design methodology research. In this paper, we first introduce some recent high level synthesis algorithms for deep sub-micron VLSI. Through analyzing them, we discuss the possible solutions for this problem.

A state-look-ahead control code transmission method

Lu Ruibing and Wei Shaojun

The 11th national conference of IC&silicon materials of China, Dalian, China, 1999

Focusing mainly on functional units, traditional high level design method is greatly challenged by wire delay in Deep Sub-Micron VLSI, since wire delay becomes the most important factor dominating circuit’s performance. In the past few years, many research results have been reported to deal with this problem. However, those algorithms only concern wires inside datapath, ignoring interconnections between controller and datapath. We proposed a new control code transmission method. Based on the geometric information from chip floorplan, the wire is separated by several registers, and thus the delay of each wire decreases greatly. Compatible with other algorithms concerning only datapath, our method can be used together with them to enhance the performance of the whole circuit.

ASIC design in ATM-SDH multiplex/demultiplex system

Zhi jun, Wei Shaojun, Chen Hongyi

Journal of Tsinghua University, Vol.39, No.S1, 1999

In order to transmit low speed asynchronous transfer mode (ATM)signal through synchronous digital hierarchy (SDH)network efficiently, a THHT97C01 ASIC in ATM-SDH multiplex/demultiplex system is designed. To design the ASIC, a VHDL based, top-down design methodology with system partition, algorithm analysis, VHDL description and synthesis etc. Is adopted. The ASIC is implemented by ALTERA FPGA for hardware verification, and is used to build a demo system. An 8-channel 25.6 M bit/s ATM transmission system through 155.52 M bit/s SDH network and its hardware structure is proposed in this article, and a complete low-speed ATM/SDH solution and a set of functional blocks for design reuse are ready for the future projects.

Header error control functional blocks for design reuse

Zhi Jun， Wei Shaojun，Chen Hongyi

Journal of Tsinghua University, Vol.39, No.1, 1999

Design reuse is very important in improving design efficiency while IC complexity increases. Functional block is one useful way for design reuse. This article describes reuse-based functional block design flow through developing the header error control (HEC) processing block set. A design flow with block modeling, algorithm analysis, structure planning, behavioral description, verification, synthesis and documentation is used to design the HEC block set. Compared with traditional design flow, this flow emphasizes model integrality, importance of different algorithm analysis for hardware implementation, generality and readability for description, and integrality of documentation. This flow fits for design reuse oriented block development, and the HEC block set can be easily reused in the asynchronous transfer mode (ATM) chip design.

Parallel Testing Based on Test Subsession Partitioning

Xiang Dong

ACTA ELECTRONICA SINICA, Vol. 27, No. 2

Consideing the fact that test response observation and test application only use a fraction of test time, a test subsession partitioning scheme is presented. Some further sources of the test scheduling problem can be used. Subcircuits in conflict in the process of test are only partially in conflict now. A new test scheduling algorthm is proposed after the test subsession partitioning scheme has been cmbined. The effectiveness to search the test scheduling solution is improved greatly by using the previous conflict information.

The Development of THRC12/13 Contactless IC Card Chip

Yang Xing-zi , Ge Yuan-qing, Dai Tie-jun,  Zhou Run-de, Gao Cheng-yun

Proceedings of the 11th national conference of Semiconductor Integrated Circuits and silicon materials, Dalian, China, 1999

This paper introduces two sort of the read-only contactless IC card chips whose work frequency are 125KHz and 13.56 MHz and which adopt EEPROM memory method. At first ,it introduces work principle and main characteristic.and then it describes the circuit design and the layout design . At last, the testing result of chips is given and the application of the card is introduced

Research on Analog Frontend of Codec Based on SD Modulation Technique

Pan Rong, Nan Deheng, Zhang Xiangmin

Journal of Tsinghua University, Vol.39, No.1, 1999

This paper describes an important part of subscriber line interface circuit in digital telephone switching systems¾¾the new generation Codec based on DSP(Digital Signal Processing) and SD modulation technologies. A novel analog frontend of a four channel Codec with second order SD modulator and CMOS bandgap voltage reference has been designed. The basic principle of  the key oversampled sigma-delta modulator A/D conversion is analyzed in detail. The circuits are simulated and verified by MATALB and HSPICE simulator with 1.2mm N-Well double-polysilicon double-metal CMOS process. The analog frontend operates on a single 5V power supply , dissipates 25mW. The die area is about 3mm².

New generation speech CODEC for digital telephone switching

Wu Xingjun, Wei Shaojun

Journal of Tsinghua University, Vol.39, No.1, 1999

In order to decrease cost and improve performance of Digital Telephone Switching, a four-channel CODEC device based on DSP was designed. In this device, oversampled analog to digital converting technique and digital signal processing technique were used. Due to these techniques, it is possible to take the advantages of digital VLSI technique, implement multi-channel speech CODEC in a single chip, and make the cost of switching low. Meanwhile, programmable digital filters were used, the performance of the system can be improved just by adjusting the coefficients of the filters by software according to different line characteristics. This device was fabricated in a 0.5um CMOS process with double poly and 3 layers metal, and integrated on a die size of 25 mm². Measurements show that all the necessary CCITT’s recommendations are fulfilled.

Implementation of an embedded montgomery modular multiplier

Zhang Wujian, Liang Songhai, Zhou Runde

Journal of Tsinghua University, Vol.39, No.S1, 1999

This paper presents an embedded Montgomery modular multiplier, It can be embedded into CPU smart card, and co-implements various public-key cryptographic algorithms based on large integers’ modular exponention. The finely integrated   product scanning (FIPS) method is used to adapt the design to the character of embedding, This modular multiplier’s throughput is highly improved by the concurrently operation of the functional units and the Ping-Pong access of the blocked RAM. At a clock rate of 10 MHz, it will take less than 40 ms to implement 512bit modular exponention using   this   modular multiplier.

A Novel Entropy Measurement on Register Transfer Level Area and Power Estimation

Zhu Ning, Zhou Runde and Yang Xingzi

Chinese. Journal of Electronics Vol.8, No.1, Jan. 1999

With the development of VLSI design methodologies, there is a need to make design estimation at a higher level. High-level estimation can provide early knowledge of the design before the circuit-level design has been specified. Using such knowledge, the designer can explore design trade-offs at an earlier phase of the design, reducing design time and cost. Recently, entropy has been used in high-level power and area estimation and presented its potential in this field. But traditional entropy calculation is based on some coarse approximation, thus making power and area estimation based on entropy less convincing. In this paper we present an accurate the output entropy of Boolean functions. We’ll show that the accuracy of the result can be controlled according to the number of terms we take in the expansion. Experiments show that the results are fairly satisfactory when we take only two to three terms. We’ll also use this new formula in power and area estimation of Boolean functional network before actual circuit implementation. The empirical results we get here are better than what has been published before, showing the validity of this approach.

Global approach for CMOS circuit optimization by transistor resizing

Zhu Ning, Zhou Runde and Yang Xingzi

Journal of Tsinghua University, Vol.39, No.S1, 1999

The power optimization has become a necessity in very large scale integration (VLSI) circuit design with the decrease of IC feature size and the corresponding increase of circuit density and working frequency. In circuit design phase delay and power can be optimized by adjusting the size of transistors, which is called ‘resizing’ . The previous methods optimized transistor sizes one cell each time individually, capable of reaching only local optima. This paper uses a new global  resizing  approach  which is based on critical paths. The sizes of cells on the critical paths are optimized simultanuously, thus further improving the delay-power product of the circuit. Moreover, by introducing delay, area and power parameters in calculation of node weight  which is used to choose candidate gates to be resized, trade-off among circuit performances can be attained. We finally integrated our method in SIS logic synthesis system and tested it using some Benchmark circuits and the results show the validity of our approach.

Speeding up Power Estimation of CMOS Sequential Logic Circuits by Circuit Simplication

Zhu Ning, Zhou Runde, Yang Xingzi

Microelectronics and Computer, No.2, 1999

Power estimation for sequential circuits is relatively hard because of the exitance of sequential feedbacks in the circuit. In the paper authors present a new approach of speeding up power estimation of MCOS sequential circuits by circuit simplication. The experimental results for some ISCAS’ 89 and ISCAS’93 circuits show that this method has the advantage of good accuracy and relatively small amount of calculation time.

Power optimization techniques in CMOS IC design

Zhu Ning, Zhou Runde and Yang Xingzi

Journal of Tsinghua University, Vol.39, No.5, 1999

This paper analyzes and compares various low-power design methods recently developed for CMOS integrated circuits, and discusses in detail the corresponding theory and methods in circuit level, logic level,  resigter transfer level and behavioral level, algorithmic level and system level, etc. Moreover, the limit of improvement for power optimization in each level and the potential for further improvement are also discussed.

Design of an RSA Coprocessor for Smart Card Application

Liang Song-Hai, Zhang Wu-Jian, Zhou Run-De, Yang Xing-Zi, Ge Yuan-Qing

Microelectronics Vol.29, No.1, Feb. 1999

Based on the microprocessor structure, an RSA coprocessor for improved Montgomery algorithm has been designed. The functional units of this coprocessor operate concurrently, and up to three instructions can be issued in one cycle. A mixed form of three-stage and two-stage pipelined structure is used for instruction execution, and the coprocessor and CPU core can share a common RAM memory through a set of switches under control. The structure of the coprocessor can be expanded to contain more than one multiplier-accumulator units for higher performance.

3.Porcessing

A study of the process experiment for SiO₂ dry etching

Lin Fayong, Liu Zhihong, Qiao Zhonglin, Zhong Tao, Lu Yong, Cao Binjun, Li Xiyou, Fu Yuxia

The 11th national conference of IC&silicon materials, Dalian, China, 1999

This paper presents a study of the process factors that effect on the thickness of the SiO₂-etched and the selectivity of SiO₂ to photoresist. According to experimental results the dependence of the SiO₂- etched thickness on the important process parameters has been formulated by the curve fitting. Under the given process conditions, the uniformity and repeatability of the SiO₂-etched thickness for the within-wafer and wafer to wafer as well as lot to lot have also been presented.

An Investigation into TDDB of Tunneling Oxide in EERPROM’s

Xue Gang, Wu Zheng-Li, Jiang Zhi, Zeng Ying and Zhu Jun

Microelectronics, Vol.29, No.3, 1999

The time dependent dielectric breakdown of tunneling oxide used for EEPR0M’s is Investigated. different accelerating methods for reliability test is analyzed and compared. Further-more, the process optimization of thin oxides is discussed

Design and Fabrication of Key Device in High-Voltage, High-Power MOS Intergrated Circuits

Wu Zhengli  Li Ruiwei  Jiang Zhi  Wang Yong  Wang Jimin

The 11th national conference of IC&silicon materials, Dalian, China, 1999

In order to increase the drain PN junction breakdown voltage of MOS transistors, this paper presents a novel device structure with a ring poly-si gate as well as an N-  region near the drain. The experiment results show that the drain PN Junction breakdown voltage of this new MOS structure can be adjusted freely between 35~70V, and it can give an output current higher than 48mA .

Some Application of Silicon PIN Detector

Zhang Jisheng, Wang Shuidi, Wang Yong, Jiang Zhi, Iiro Hitetanen, Mikko Matiforala

The Proceedings of the 11th National Conference of IC and Silicon Material, Dalian, China, l999

Super low leakage current PIN diode was developed by IMETU and DT Co. The PIN Diode can be used as a detector which offers an extensive range of high-quality products to serve your critical light and radiation measurement needs. The Diode has got market in Europe and USA. In the paper, introduce some potentia1market in China. Some companies has contact with us. Both side hope to develop some instrument such as NDT (Non destroy testing) in industry. The principle of these instruments is introduced too.

Research of the blank area effect created by refraction of photoresis on the step of Wafer surface.

Wang Jimin  Li Ruiwei

The Proceedings of the 11^th National Conference of IC and Silicon Material, Dalian, China, 1999

when a step is on the surface of wafer, due to refraction of photoresis, a blank area of exposure will be created near by the step and therefore the residue of photoresis after developing .In this paper, we provide a set of analytics equations which indicate the relationship between size of volume of the residue and step angle, thickness of photoresis. There are results of simulation for lithography process in this paper. To deducing the volume of the residue, the size of the step angle will be reduced to the volume under a threshold, and when there are lines with smell spaces and parallel with the step, the lines must lift the step.

With computer aided analyzing characteristic and parameter of LDMOS device

Wang Jimin

Journal of Tsinghua University, Vol.39, No.4, 1999

This paper uses a group of analyses equations to describe the relations in the parameters of Lateral Double Diffused MOS (LDMOS) device. Equations are solved to get I - V curves of different VG including V_G - I_D curve in the area of subthreshold and the phenomenon of dynamic negative impedance on the drain. In different operating situations the paper offers the distributions of electric field, electric potential, shift and diffusion current in the channel.  Complex mechanism of saturation is calculated and analyzed and the original  pinch off voltage depended on the electric field in pinch off point is proposed . Calculation method and a set of curves are offered.  Paper explains the negative impedance and other characteristics using the distribution of electric field in the channel.

Current Analysis of FLASH during Erasing and Writing Process

Liu Yin, Zhu Jun, Zeng Ying, Jiang Zhi

Microelectronics & Computer, Vol.16, No.3, Jun. 1999

This paper will discuss the erasing and writing process of nonvolatile memory devices FLASH. A new simulation model of current during its erasing and writing process is also presented. At last, some experiments of FLASH manufactured in our processing line testify the theory and simulation model.

Structure and function research on FLASH memory

Liu Yin, Su Li, Zhu Jun

Journal of Tsinghua University, Vol.39, No.S1, 1999

This paper proposed a novel device of FLASH and introduced its manufacturing processing. Following the processing simulation, device simulation related to the writing operation based on Hot-Electron-Injection(HEI) and the erasing operation with F-N tunneling effect was completed. The program times were determined by variation of charge quantity on float gate with time to satisfy threshold voltage window. A current model with theory equation was established to analyze the relationship between substrate current and variation of threshold voltage with constant electrical field in ultra-thin SiO2 during the writing progress. In this case substrate current can reflect variation of threshold voltage.

4.CAD and CAT

Semiconductor Device Electro-thermal Simulator and Its Application

Tian lilin, Hao Ming

Journal of Tsinghua University, Vol.39, No.S1, 1999

This paper presents an electro-thermal device simulation program which is based on the Dual Energy Transport model, consists of the energy change due to the thermal diffusion of lattice and the generation-recombination of carries, and considers the influence of energy flux of carries on the thermal system. According to the characteristics of electro-thermal simulation, two new methods, group decoupled (group Gummel) method and different time step method, are realized in this program. The calculation speed of group decoupled method is 2 or 3 times of that of the traditional method and the memory space of the former is only half of the later. This program has been integrated into device simulator PISCES-2H. The results of negative resistance effect and transient characteristics of a SOI structure prove that the program can correctly simulate the main phenomena caused by self-heating effect.

Stress analysis with Java in two-dimensional oxidation with Java.

Dong Ning, Tian Lilin

The 11th national conference of IC&silicon materials of China, Dalian, China, 1999

As a rising OOP language, Java is being widely used in the field of scientific computing. A program of FEM for stress analysis in two-dimensional oxidation with Java is presented in this paper. The result is compared with that of SUPREM-IV and some conclusions are discussed.

New Analytical Model for Deep-Submicron MOS Circuit Simulation

Zhang Wenliang, Tian lilin, Yang Zhilian

CHINESE JOURNAL OF SEMICONDUCTORS, Vol.20, No.2, Feb. 1999

A new model for deep-submicro MOSFET is developed, which includes various second-order physical effects in the operations of deep-submicro MOSFET’s.In the model, a  unified formula is used to describe all the operation regions, which keeps the model C_∞-Continuous. The model is suitable for both digital and analog MOS circuit simulations. A good fitting has been achieved between the model and experiment data.

A tool for automatic logic parameter extraction

Chen Shuilong, He Xiangqing

Journal of Tsinghua University, Vol.39, No.S1, 1999

In order to shorten the development cycle of establishing logic parameter library and to diminish the errors caused by manual extraction, an automatic tool to extract logic parameter is proposed. A logic simplification and one dimension binary edge search methods are used for automatic SPICE waveform generation and logic parameter extraction of circuit cells. The tool can generate waveforms for SPICE input according to user timing specifications, extract the logic parameter and create the data book for library cells automatically. The results can be transferred to SYNOPSYS and CADENCE formats. It can be applied to extract logic parameters for circuit cell and establish logic parameter library.

Automatic waveform generation technique for a special sequential circuit in logic parameter extraction

Chen Shuilong, He Xiangqing

The 11th national conference of IC&silicon materials of China, Dalian, China, 1999

This paper proposes an automatic waveform generation technique used for SPICE simulation when extracting logic parameters for a special sequential logic circuit. This technique can be used to generate SPICE stimulus waveforms for these special sequential logic circuits quickly, speed up the logic parameter extraction process and guarantee a proper SPICE simulation waveform for logic extraction.

A labeled method for polygon partitioning.

Chen Shuilong, Yang Zhilian, He Xiangqing

CAD/CG’99 International conference. Shanghai Jiaotong Univ., China, 1999,Dec，

In this paper, a labeled method is proposed to decompose polygons with some non-Manhattan edges using horizontal cuts or vertical cuts in VLSI net extraction. The horizontal or vertical cuts are according to the number of horizontal and vertical candidate cuts of a polygon. This method reports non-overlapping trapezoids whose union is the polygon. The time complexity is O( n*k ), where n is the number of vertices in the polygon and k is number of vertex being cut.

Development of Layout Compiler for Semi-Regular Circuits based on C Language

Zhang Jianjie , Yang Zhilian

Microelectronics,Vol. 29 ,No. 4, 1999

In this paper, the basic methods for describing structure of Semi-Regular circuits layout using C programming language are discussed. The basic steps used for putting leaf cells together into larger cells and the general methods for programming layout compiler of Semi-Regular circuits are worked out. Using our methods, one can rapidly construct a given type layout compiler after the layouts of leaf cells and entire structure have been built.

Analyzing Short Channel Effects in Deep Submic ron MOSFET’s Using Variational Method

Chen Wensong, Tian Lilin, Li Zhijian

Journal of Tsinghua University, Vol.39, No.S1, 1999

Short channel effects will eventually preclude further MOSFET miniaturization. To solve the Poisson’s equation involved in short channel effects analysis, variation method is applied. And the expression of the key parameter called natural gate length scale is obtained, which includes the 2-D effects in gate dielectric, channel depletion layer and buried oxide. It is only related to the difference between the boundary condition and long channel solution, thus has clear physical meaning. Comparisons of the short channel effects for uniform channel doping bulk MOSFET, intrinsic channel doping bulk MOSFET, conventional SOI MOSFET and double gate SOI MOSFET are all conducted using our model, and the results are verified by 2-D numerical simulations. So it is confirmed our model can correctly simulate subtle differences in different structures, and gives a guidance for new device structure design with suppressed short channel effects.

Design and Implementation of a Circuit Level Electro-thermal coupled Simulator

Chen Wensong, Tian Lilin, Li Zhijian

The 11th national conference of IC&silicon materials of China, Dalian, China, 1999

With the down-scaling of MOS transistor, the power density of the IC increases notably. This results in non-homogeneous temperature distribution for the whole circuits, which can not be solved self-consistently using commercially available simulation tools. Based on conventional circuit simulator SPICE, we develop a circuit level eletro-thermal coupled simulator. Applying electrical and thermal network as input file, we can simulate the self-heating and cross-heating effects in the state-of-art circuits. Static and dynamic thermal coupling simulations are all realized in our implementation, and it’s ability is demonstrated by a few typical cases.

Analyzing Short Channel Effects in Deep Submicron MOSFET’s Using Variational Method

Chen Wensong, Tian Lilin, Li Zhijian

The 11th national conference of IC&silicon materials of China, Dalian, China, 1999

Using variational method to solve the Poisson’s equation involved in short channel effects analysis, the parameter called natural gate length scale is obtained in this paper. Comparisons of the short channel effects for uniform channel doping bulk MOSFET, intrinsic channel doping bulk MOSFET, and SOI MOSFET are all conducted using our model, and the results are verified by 2D numerical simulations. So it is confirmed our model can correctly simulate subtle differences in different structures. Because our deduction includes all the 2D effects in gate dielectric, channel depletion layer and buried dielectric, the validity of electrical equivalent oxide thickness approximation can be investigated using this model. The results show that it is only valid when gate dielectric constant is relatively small.

Design and Development of IC Fabrication Process MCAI System

Xiang Cailan;Kong Xiaohua;Wu Bo;Dong Jihua;Zhu Zhengyong;Tian Lilin;Song Wenzhong

Journal of Tsinghua University, Vol.39, No.S1, 1999

This thesis reports a CAI system of IC fabrication process instruction, which is developed in multimedia. It also discusses the importance of applying the multimedia technology to the instruction, introduces the main process of system development, and summarizes the structural design and multimedia materials collecting and making in this system.The subsystems were finished this May, and can run separately. Now the whole CAI system is in the step of debug. It will be put into formal use in Tsing Hua University in fall, 1999, and will have its version on the web. Its successes in institution can be expected.

A computer-aided manufacturing system for integrated circuit– XHCAM

Zhan Guo, Cailan Xiang, Xiaohua, Kong

Microelectronics and Computer, Vol.16, No.5, 1999

This paper introduces a computer-aided manufacturing system for integrated circuit, named XHCAM, sharing such attributions as applying for great yield, completed functions, easy use, and low cost.

Two-Dimensional Numerical Simulation of Float Plates

Zhang Min，Li Zhaoji

Chinese Journal of Semiconductor, Vol.20, No.4, Apr. 1999

A new method of the float field plates simulation is presented, based on simulation of the heterojunction device. It uses a material of zero conductivity and the permittivity of 3.9 instead of the material SiO2.The two dimensional numerical simulation of a novel float field plates is performed by this way, and the results is preliminary supported by experimental resultes.

Design of Float Plate Using Automatic Layout Generator

Zhang Min，Li Zhaoji

Chinese Journal of Semiconductor, Vol.20, No.8, Aug. 1999

Based on the data structure of the layout format CIF, a layout automating generator of the high voltage and power device is developed in this paper, and a layout of the 6000V power LDMOS transistor with double layers of floating field plate is designed by it. By the experimental test the results are satisfied with the design expectation. The power device design expectation. The power device design cycle is decreased significantly by this method when the optimum cell size of the device is determined.

The mixed-mode Simulation of High Voltage LDMOS Switching Circuit

Zhang Min，Li Zhaoji, Yang Zhilian

The 11th national conference of IC&silicon materials of China, QingDao，China，1999

The general circuit simulator only has a certain low voltage device models. It is impossible to simulate the ICs which include high voltage devices. In order to analyze the influence of the power device on the circuit performance and the parasite effects on power devices, we mixed the SPICE3F5 and PISCES2B and performed the mixed-mode simulation of the power IC.

5.Others

A testing system of IC card based micro-processor 8051

Li Guoxin, Yang Zhaomin, Zhang Zhonghui

Journal of Zhejiang University , Vol.32, Dec. 1998

A kind of testing system of IC card, taking HXL768 as an example,is introduced in this paper. The system is based on 8051 microprocessor. The configuration of the circuit is described in detail. The programming of software is also included.

Oveview of Contactless Card Technologies

Yang Zhaomin  Zhang Zhonghui

Computer Engineering and Application, Vol.35, Dec.1999

The contactless card technologies and general situation at home and abroad were introduced in this paper. Lastly,three kinds of typical contactless cards were presented.

Contactless IC Card Technologies

Yang Zhaomin

SMART CARDS CHINA‘99 CHINA ,SHEN ZHEN, Apr. 1999

Operation principle,international standards and applications of contactless cards were introduced in this paper. Development of Combination Card abroad also was introduced. Lastly，sevelel kinds of typical contactless cards were compared.

The Technology Roadmap for Microelectronic Packaging and CSP

Jia Songliang

PCB & SMT, No.8, Aug. 1999

This paper introduces the roadmaps for microelectronic technology and their packaging,and the chip scale package(CSP)

Development and Current State of Electronic Packaging for Surface Mount Technology

Wang Weiling, Jia Songliang

Civilian Technology & Products Transferred from Millitry Aviation industry, No.10, 1999

An overview of the current state and progress of the advanced electronic packaging, i.e.Ball Grid Array (BGA)Chip Scale Package(CSP), Direct Chip Attach(DCA), for SMT is given in this paper.

Design for Microelectronic Packaging

Jia Songliang

The Proceeding of ‘1999 National Conference on Electronic Packaging, Shanghai, China, 1999

It’s a invited talk.This peper briefly introduces electrical design.thermo-mechanical design for microelectronic packaging, and computer aided design (CAD) in packaging.

Thermal Stress Analysis in the Package of the Power Devices

Xuemei Wang, Xuewei Sun, Songliang Jia

The Proceeding of ‘1999 National Conference on Electronic Packaging, Shanghai, China, 1999

Packaging failure and cracking occur very often if sufficient large thermomechanical stresses are built up in the electronic packaging. Such stresses are formed during manufacturing process due to the change of temperature and the thermal mismatch between different materials.So a simple but accurate method of estimating thermal stress is needed in package design. Usually, numerical analysis is convenient but efficient for estimation stress. This paper provides a 3Dmodel to analyze t