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Division of CAD Research (Publications)

1. Introduction
The research fields in the CAD Research Division include semiconductor device physics and VLSI CAD. The main research topics are: the carrier transport models in scaled-down MOS devices, CAD software development for micro- and nano-devices, new structures for micro- and nano-devices, methodology for developing IP library and development of IP cores for memory used in SOC design, layout-based extraction and verification of RF circuits, the computer-aided manufacturing system (CAM) for IC fabrication and development of integrated biologic sensor . There are currently 14 research projects being undertaken in the Laboratory, and they are: 3 national basic research (973) projects, 2 national high-tech development research (863) projects, 3 major project of National Natural Science Foundation (NSF), 2 project funded by Beijing Municipal Government, and 4 projects with industry both inside of China and internationally.

CAD Research Division provides 7 undergraduate courses and 2 graduate courses.

There are 11 faculty members and staff in CAD Laboratory: 5 full professors (YU Zhiping, TIAN Lilin, HE Xiangqing, XIANG Cailan, WANG Yan), 2 associate professors (ZHANG Wenjun, ZHANG Jinyu), 1 lecturers (ZHANG Li) and 2 engineers (SONG Wenzhong, GUO Xingming).

 

Director:

Prof. WANG Yan

Phone: +86-10-6277- 2373

FAX: +86-10-6277-1130

E-mail: wangy46@tsinghua.edu.cn

Vice Director:

Associate Prof. ZHANG Wenjun

Phone: +86-10-6277- 1577

FAX: +86-10-6277-1130

E-mail: zwj@ tsinghua.edu.cn

 

2. Research Projects and Graduate Education in 2005

There are total 19 research projects being undertaken by CAD Laboratory in 2007, the faculty members of this Laboratory head 7 of them.

There are 9 Ph.D. students and 15 MS students working for their theses in CAD Laboratory. In addition, there are 18 undergraduates (seniors) who completed their graduation dissertations in the Laboratory.

 

Project

Name

Funding Source

Principal Investigator

01

20-50 nanometer devices and correlative physics problems

¡°973¡± project

Tian Lilin

02

Modeling and simulator development for 20-50 nanometer devices

¡° 973¡± project

Yu Zhiping

03

Next-generation devices of compound semiconductor

¡° 973¡± project

WANG Yan

04

Quantum transport and high frequency properties research for CNT

¡°973¡± project

Zhang Jinyu

05

Circuit model and parameter extraction for Sub-90nm MOSFETs

¡° 863¡± project

YU Zhiping

06

Accurate extraction and analysis of RF circuits based on the layout design

¡° 863¡± project

Zhang Wenjun

07

Research on high-speed and low power dissipation device used in SOC

NSF

ZHANG Li

08

Network setup and research for International computational nanoelectronics

NSF

Yu Zhiping

09

Design method on SOC signal integrity and mixed signal and radio frequency circuits

NSF

YU zhiping

10

Nano-meter Semiconductor Devices Quantum Transport Model

Education Foundations

Yu Zhiping

11

Nano-meter Science and Technology

Education Foundations

Yu Zhiping

12

The Management System of General Design Module£¨IP£©

Beijing Municipal Government

Xiang Cailan

13

Joint Research Agreement of Universities

International Cooperation

Yu Zhiping

14

Joint Research Plan for Nanometer Device Modeling

International Cooperation

Yu Zhiping

15

ESD Devices Modeling of RF Circuit and Circuit Simulation

International Cooperation

Yu Zhiping

16

Quartz crystal simulation

International Cooperation

Yu Zhiping

17

Research on High-frequency CMOS Circuit Model

International Cooperation

Yu Zhiping

18

Research on 3D Mask Effect Simulation

International Cooperation

Zhang Wenjun

19

Design & program of WEB IC-CAM

Industrial contract

Xiang Cailan

*NSF: National Natural Science Foundation ( China )

 

3. Research Description

1) Transport Mechanism and Modeling of Ultra-Small MOS Devices

Researched of Quantum Hydrodynamic model (QHD) and get the convergent result for the coupling functions and a negative differential resistance (NDR) is found at 77K, some device structure are simulated using QHD to verify the quantum effects when the device scale comes less than 100nm. Researched on 90nmCMOS device¡¯s electrical-behavior simulation based on Taurus-Device and ISE DESSIS, cooperating with TMSC. Programmed with MATLAB, the 1-D Poisson and Schr?dinger Functions were solved self-consistently, which provides the boundary conditions for real 2-D ballistic quantum transport device model. Finished the discretization of 2-D Double Gate MOSFET model using Finite Element Analysis (FEA) Method. 2-D Poisson and Schr?dinger Functions were solved self-consistently using Broyden-Newton iteration. We have implemented a hybrid 3-D quantum mechanical model based on NEGF method for Ultra-thin channel FinFET device and Nanowire. We have simulated FinFET device sub-10nm and analysised the quantum confinement and ballistic tunneling effect on device characteristic quantificationally. The 3-D quantum potential modified transport model for silicon devices using Density Gradient theory has been implemented.

 

2£©The research of mobility model

For the microscopic simulation of holes mobility in the strained silicon inversion layer, a self-consistent 6-band k dot p method for the electronic subband structure of the confined holes is applied, and the Matlab program for the self-consistent solutions of quantized subband wavefunctions and energies has been completed. We are debugging the program and collecting the data of band structures. Moreover, we have established the scattering mechanisms considered in our case, including acoustic phonon, optical phonon, surface roughness and coulomb scattering. The calculations of scattering rates will be completed in terms of the self-consistent results provided by Matlab program.
Compared with traditional Si MOSFET£¬the novel MOSFET structure with strained Si and SiGe as channel layer have been used in many cases. The stress induced mobility enhanced effect was studied in strained Si and SiGe layer in the base of deformation potential theory. A hole mobility model considering the effect of valence band shift and effective mass change was deduced and embedded in the 3-D simulator TaurusDevice. Then, the I-V characteristics of strained Si and SiGe MOSFET were calculated according to this model. The results show that strained Si and SiGe MOSFET have better performance than that of traditional Si MOSFET

 

3£©Research and Development of Simulators for Heterostructure Semiconductor Devices

Taking account of diffusion and drift movement simultaneously, a charge controlled analytical DC formula was derived, Ids-Vgs and Ids-Vds curves are calculated. This formula can be incorporated into Spice simulator. The parameters of Small signal equivalent circuit of GaN HEMT are extracted. We begin to research the current collapse effect and the mobility model in AlGaN/GaN HEMT

 

4)New Device Structures

We have accomplished the following projects in this year: 1) Based on the process analysis and simulation, the off-state current (Ioff) and the ratio of on-state current to off-state current (Ion /Ioff) for Drain and Source On Insulator (DSOI) are optimized at the same time. This work is helpful to the new DSOI MOSFET design. A new buried oxide device structure has been proposed. Ion of the new structure device is 3.3e-4A/um, Ioff is 9e-16 A/um, and Ion /Ioff are 3.6e11. Compared with the former DSOI MOSFET, the new structure decrease Ioff significantly and maintains Ion at the same time. Therefore, Ion /Ioff have increased an order than the former. 2) Rely on the simulation and optimization, the process for fabrication of self-aligned DSOI nMOSFET is been proposed. 3) The self-aligned DSOI nMOSFET is been tape out in 0.8um baseline. 4) After measured the device on prototype and primary analysis, the process for fabrication of self-aligned DSOI is viable.
We have measured the polysilicon film¡¯s thermal conductivity. Based on the steady-heating method, undopping polysilicon film¡¯s thermal conductivity has been measured from 300K to 400K. The film¡¯s thickness is 200nm and 260nm respectively. From the measurement result, the thermal conductivity of the films decreased when the thicknesses become thinner, and the thermal conductivity slightly varied with the temperature.

 

5) Design of SiGe based Spin-FET Structure and Monte-Carlo Simulation

A semiclassical Monte Carlo model was utilized to study the spin-polarized transport properties in modulation-doped Ge channel Spin-FET, and the spin-polarized properties, including the spin scattering length and the spin polarization, were investigated. The results from Monte Carlo simulation provide appropriate device structure and optimal parameters for the realization of Spin-FET.

 

6)Analog Layout Automation

A method to partition a CMOS analogcircuit to extract symmetrical layout constraints of the circuit is presented1. We implement it as a program that will be a part of an automatic analog circuit layout constraints extraction tool. To find the symmetrical parts in an analog circuit and transform them as layout constraints to the automatic placement/route tool is the main function of the implemented program. A partition algorithm similar to that of comparison method once used to verify the circuit layout against the netlist of the circuit is used for our purpose. The labeling/relabeling process of that method is changed by combining the consideration of the direction of signal flow in the circuit. Experimental results demonstrated that our method is sufficient and effective for analog circuit symmetrical layout constraint extraction.

 

7)Development of IP Cores and Cell Library

A 2K*8bits EEPROM memory, which operates with a single 3.3V power supply based on 0.35¦Ìm CMOS process, has been developed. Several key design techniques are summarized. An improved read out circuit that consists of SA (sense amplifier), bit line decoding and word line charge/discharge circuit to minimize the read access time, is described particularly, as well as the approach to optimize the program operation. Placing great emphasis on the on-chip high voltage generation circuit, a zero threshold voltage charge pump is proposed, which can improve the performance without additional design and process complexity. A 40ns typical read access time and 2ms page programming time are achieved. The cell size is 11.27?m2 and chip size is about 1.5mm2. The chip was delivered to tape out after verified by design rule check and simulation, fabrication in SMIC is finished. Now the testing is in process by J750 of Huada testing center.
The goal is to establish a Management System of General Design Module £¨IP£­Intellectual Property £©£¬ which achieves Management and trade of IP data in internet. Related hardware and software have been purchased. The basic Management System of General Design Module has been installed, and most of them work normally. The research of IP Core standards is accomplished, and the model entity in database is fully analyzed. Also the model design is partly accomplished, and a standard management template of IP Core is established. Through lots of researches of many materials about the security of data in internet and plenty of demonstrations of many schemes, the ECC arithmetic is chosen to encrypt the IP data package and the AES arithmetic encrypt the exchange password.
The layouts of 0.6¦Ìm standard cells have been improved and optimized on the layouts design rules used in SGNEC. Then the 0.6¦Ìm standard cells have been verified all of these drawings on Layout and Logic (using the tools of DRC and LVS) for enhancing the veracity and reliability. To test the standard cells, using Cadence system, which has the characteristic of high efficiency in placing and routing automatically, an example IC layout will be designed with the standard cells. This IC example has been put into production and the full functional testing of the chip proves that design is successful.

 

8) Layout-based Extraction and Verification of RF Circuits

The project is to develop a system of verification and synthesis for RF circuits. The prototype tools finished in this project are: A prototype system for generation of layout-based scalable SPICE model with parameter extraction; A program which processes the S-parameters in the frequency domain and generates a SPICE circuit model with all element values; A KBNN-based program package which takes layout data and technology file and generates the S-parameters in the frequency domain; A prototype of spiral inductor synthesizer. We use the neural network approach to build the working platform.
We solve the passivity issue for linear passive networks, such as RF spiral inductors. By analysis of the passivity condition, we put forward a novel and simple ¡°local compensation¡± approach for two-port network and an iterative algorithm based on linearized discriminant function.
We developed a 3-D capacitance extraction algorithm based on multi-layered Green function. The algorithm can efficiently compute and store the multi-layered Green function, thus it can accurately handle the lossy substrate in nowadays RF CMOS technology. It can also easily handle true 3-D structures, and only the conductor surfaces need to be discretized.

 

9)IC-CAM System

In end of 2003£¬a new generation of computer-aided manufacturing system for integrated circuit has been developed and is used in Microelectronics R&D Center Chinese Academy of Sciences. The B/S system - WEB IC-CAM is developed independently by our country. On the basis of original developed IC-CAM systems£¬web data publication function is added. And the web-based report form function is realized for the first time. Having achieving great economic and social benefits

 

10) Device Modeling and Model Parameter Extraction

According to the measurement results of P-well Si/SiGe resonant tunneling diode fabricated by the novel device division of institute of microelectronics, the DC parameters extraction of RTD was carried out from I-V relationship considering the effect of series resistance. These parameters can be incorporated into Spice simulator to design RTD-based circuit.

 

11) Design and development of integrated biologic sensor

Combination of DNA molecules, electrical characteristics of whole system is changed, so if a voltage is added on the system, a relatively large current will be generated. According to above, we combined it with our low cost, large scale integrated circuit to implement a brand new biosening system which can discriminate a large number of DNA molecules from a mixed solution or other samples. Definitely, it exhibits a charming prospective in the future. We have deliberately designed and analyzed our circuit combined with wordline and bitline decoders. Especially, the cell array, read and write passages are considered. All the parts of our circuits have been simulated and emulated by HSPICE, most of layout has been finished. Our on chip integrated small signal amplifier and cell array are being optimized at present, which construct our most significant parts.
About the amplifier, we used LBT, enhanced gain and magnify scales of key transistors to decrease 1/f noise and thermal noise; Used increasing biasing symmetry and match of transistors to enhance stability of gain. Also, we have optimized the paradox between stability of gain and speed to attain higher performance. At present, our testing circuit is being fabricated in SMIC. About the cell array, we departed the read, write passages and forward, reverse operations to obtain more dependability; Optimized scales of transistors and imported dummy transistors to decrease the current generated from charge implantation when switching cells. We are busy generating layout of this part and the whole system to experiment and fabricate in SMIC in near future.

 

4¡£ Recent Publications

      2005

      2006

        2007

        2008

5. Teaching

The courses provided by CAD Laboratory in 2007 for undergraduate and graduate students are as follows:

Course

Name

Level

Hours

Lecturer

1

Solid State Physics

Undergraduate (compulsory)

64

WANG Yan

2

Semiconductor Physics

Undergraduate (compulsory)

64

TIAN Lilin

3

Semiconductor Devices

Undergraduate

(compulsory)

48

ZHANG Li

4

IC CAD

Undergraduate

 

48

ZHANG Wenjun

5

IC Processing

Undergraduate(compulsory)

 

32

XIANG Cailan

6

Semiconductor Sensors

Undergraduate

 

32

XIANG Cailan

7

VLSI IC-CAD

Graduate

48

YU Zhiping

8

Nanoelectronic Devices

Graduate

 

32

WANG Yan

9

The Invention of the Transistor and the Birth of the Information Age

 

Freshman Seminar

 

16

YU Zhiping

 

All courses are given using multi-media. Two textbooks from famous foreign universities have been translated into Chinese; they are Device Electronics for Integrated Circuits and The Design of CMOS Radio-frequency Integrated Circuits.

 

Address£ºInstitute of Microelectronics,Tsinghua Univ. Beijing,China¡¡Post Code£º100084
Tel£º86-010-62782712¡¡Email£º