Division of IC & System Design

1. Introduction
Division of Integrated Circuits and System Design is engaged with education and research in System on a Chip(SoC) design and test, including theory, algorithm, methodology and architecture. Some laboratories are associated with the division: first is "Electronic System and Special Integrated Circuit Technology Research Center" that is supported by the "211 project" of Educational Ministry of China, second is "Cooperation Research Center on IC Design On-line" that is supported by Educational Ministry of China, third is "State Integrated Circuits Professional Education Base at Tsinghua University", fourth is "Tsinghua Zhongxing Joint Research Center of Integrated Circuit Design" that is supported by city government of Beijing. The software and hardware environment advanced and perfect for IC design and test.

2. Staffs
Director:
Zhang Chun
Tel: (86)-(10)-62792912
Fax: (86)-(10)-62795104
Email: zhangchun@mail.tsinghua.edu.cn
Vice Directors:
Liu Leibo
Tel: (86)-(10)-62795097
Fax: (86)-(10)-62795104
Email: liulb@mail.tsinghua.edu.cn
Chi Baoyong
Tel: (86)-(10)-62795096
Fax: (86)-(10)-62795104
Email: chibylxc@mail.tsinghua.edu.cn

There are 8 professors, 10 associate professors, 12 lecturers or engineers and 1 post doctors in the division. There are also 123 master candidates and 37 doctor candidates, respectively 86 in 2007.

3. Researches

The researches of the division focus on the design and test of SOC . There are three main directions and each of them can be separated into several branches:

(1) General Processor

•  Micro-controller with Reduced Instruction Set Computer (RISC).

•  Digital Signal Processor (DSP).

•  New concept and theory of low power consumption for digital circuit design.

(2) Analog and Mixed Signal (AMS)

•  CMOS Radio-Frequency (RF) front-end circuits.

•  Theory and technology for the design of high precision mixed-signal integrated circuits.

•  ADC and DAC circuits.

•  LCD/OLED display controller.

(3) Application of System On a Chip (SoC)

•  Information security system.

•  Wireless Local Area Network interface system.

•  Methodology for SoC design and test.

4. Projects

(1) Research on key techniques of SoC design service---IP protection system based on watermarking technique

Sponsor: Beijing City Government

Duration: From September 2006 to December 2007

ID number: D0306008040811

Manager: GAO zhiqiang

The project develops a kind of IP protection system that can provide a series of all-round, multi-level IP protection solutions. The fulfillment of the system is mainly based on several core techniques as follows: Symmetric encryption technique, asymmetric encryption technique, watermarking technique, network certification and feedback technique. The system can be divided into two parts by function: One part is encryption and decryption, feedback and supervision, the other is watermarking protection.

(2)Investigation of Battery-less TPMS for Automobile

Sponsor: NXP

Duration: From 2007 to 2008

ID number: 041902013

Manager: WU Liji

The project aims to investigate the technologies of implementing battery-less tire pressure monitoring system (TPMS) having applications in automobiles. The work includes a survey of potential technologies for battery-less TPMS, an intensive investigation of the battery-less TPMS with external power injection, Kinetic-energy, and SAW based TPMS, the evaluation of the cost and performance of battery-less TPMS.

(3) Research on fractional-N frequency synthesizers for WCDMA applications

Sponsor: IBM, USA

Duration: From July 2007 to June 2008

ID Number: H100002002

Manager: RHEE Woogeun

Performance, hardware complexity, and power consumption are key design trade-offs in fractional-N frequency synthesizer design. This project studies various frequency synthesizer architectures for WCDMA applications. A low cost finite-modulo fractional-N frequency synthesizer is designed in IBM 180nm RF CMOS while a high-performance fractional-N frequency synthesizer is implemented in IBM 90nm RF CMOS. Two different architectures are investigated, and performance comparison is to be made based on experimental results.

(4)Direct-digital phase modulation in polar transmitter design for GSM/EDGE and beyond

Sponsor: Samsung, Korea

Duration: From June 2007 to May 2009

ID Number: H041902008

Manager: RHEE Woogeun and WANG Zhihua

This project is toward building a high performance 8-PSK/GMSK polar transmitter for GSM/GPRS/EDGE, the architecture of which can be reconfigurable and extended to WCDMA/3GPP LTE applications. By employing direct phase modulation using a wideband fractional-N synthesizer and a pre-distortion filter, one of the lowest power consuming approaches can be realized for the polar modulation. This research will strive for the best system solution for low cost, low power transmitter design.

(5) All-digital clock-and-data recovery system with a precise delay line

Sponsor: Samsung, Korea

Duration: From June 2007 to May 2009

ID Number: H041902007

Manager: RHEE Woogeun and WANG Zhihua

All-digital clock-and-data recovery (CDR) system gets higher attention than ever since it does not require analog loop filters. The all-digital CDR, however, suffers from the design trade-off between jitter tolerance and phase resolution. A fast phase capture time is highly desirable in many serial link I/Os including memory systems. This project is to build a high-performance low-power all-digital CDR for high-speed (>4Gb/s) serial links, the architecture of which can be reconfigurable for general clocking applications.

(6) Low-noise fractional-N frequency synthesizer design for WiMAX/WLAN applications

Sponsor: FCI, Korea

Duration: From June 2007 to May 2009

ID Number: H041902009

Manager: RHEE Woogeun and WANG Zhihua

The project studies the key technology of integrating a fractional-N frequency synthesizer for 4th-generation (4G) wireless applications. In OFDM-based 4G wireless standards, the integrated phase error of as low as 0.5 degree-rms is required. In this project, a low noise multi-standard frequency synthesizer design is investigated and implemented in TSMC 90nm RF CMOS.

(7) The module design and VLSI implementation of modular exponentiation multiplication for large integers

Sponsor: The ministry of science and technology of China 863 project

Duration: From Jan. 2007 to Dec. 2008

ID number: 2006AA01Z418

Manager: Li shuguo

This project studies the key technology of modular exponentiation multiplication and its implementation, emphasis on the fast implementation of modular exponentiation multiplication on RSA algorithm and GF(P) Elliptic Curve Cryptography. The main contribution is to propose a new algorithm of modular multiplication for large integers on RSA and ECC, and a new VSLI architecture for large integer multiplier to implement the modular multiplication algorithm for final RSA and ECC application.

(8)Design of UHF RFID Tag IC according to ISO 18000-6 Type B/C

Sponsor: National High-Tech Research plan (863 Plan)

Duration: From December 2007 to December 2009

ID number: 2006AA04A109

Manager: Wu Xingjun

This project aims to develop UHF RFID Tag IC according to ISO18000-6B/C standard, and studies the key technology of verification, testing methods, reliable and quality control for mass production.

(9)Design and research of implantable wireless circuit stimulator

Sponsor: National Key Basic Research and Development program (973 program)

Duration: From June 2007 to December 2008

ID number: 2005CB724302

Manager: Zhang Chun

This project aims to develop implantable wireless circuit stimulator for vision prosthesis. The integrated circuit is composed of wireless transceiver, digital-to-analog converter, switching matrix, circuit stimulator. It can provide multi channel and multi mode stimulus, fulfill the requirement of scientific research of vision prosthesis.

(10)Research on related techniques of NoC design

Sponsor: Research Fund for the Doctoral Program of Higher Education(SRFDP)

Duration: From January 2006 to December 2008

ID number: 20050003083

Manager: SUN Yihe

The object of this project is the methodology of application-specified NoC design. It includes the abstraction of application communication, the rule description of a specified network, the design of any topologies suitable for various applications, the network design space exploration, the auto-generation and evaluation of network program protocols, the hardware ( RTL code ) generation, and the design and simulation of specified application communication model. Moreover, a protocol chip will be developed to verify the validity of proposed methodologies.

(11)Development of a CdZnTe nuclear detector readout ASIC

Sponsor: Department of Engineering Physics Tsinghua University

Duration: From February 2007 to December 2008

Manager: SUN Yihe and LI Xiangyu

This project is going to develop a CdZnTe nuclear detector readout ASIC. The CdZnTe detector is a kind of common nuclear signal sensor. And the ASIC to be designed is the analog front-end of a nuclear detection system, which converts the charge on the detector into a voltage pulse, which is amplified with shaping and fed to the subsequent measurement part. It is the key component of a nuclear detection system and is widely used in high-energy physics experiments, nuclear diagnostics and so on fields. The whole chip includes a low-noise charge-sensitive preamplifier, a shaper filter and a output driver. Our work will research the singlechip integration of this system base on the 0.18 micron CMOS technology.

(12)Ddiver and module for OLED color display

Sponsor: Ministry of information industry of PRC

Duration: From June 2004 to December 2006

ID number: [2004]42#-12

Manager: CHEN Zhiliang

Compared with LCD, OLED has a lot of advantages. To master the advanced technique of the driving and controlling IC for the color OLED panel, including circuit design, layout design, test, package and etc；To establish an IC development platform for the OLED display driver and controller which has our own IP；To design and fabricate color OLED panel drivers and controllers applied in cellphone, PDA and etc；To establish an industry chain for the IC design, manufacture and application of the FPD driver and controller, with the cooperation of the panel manufacturer.

(13)Research on the HW/SW co-design methodology of embedded reconfigurable SoC

Sponsor: Nature Science Foundation

Duration: From January 2007 to December 2009

ID number: 60676012

Manager: Wei Shaojun

Based on the SoC design methodology, embedded system design, optimization theory, this project studies the methodology of embedded SoC design, utilizing the HW/SW co-design strategy. By establishing the HW/SW co-simulation, co-verification as well as co-development platform, this project tends to propose a HW/SW co-design method in reconfigurable embedded SoC design in order to solve several key problems in embedded system.

(14)Algorithmic Structures of Elliptic Curve Cryptosystems and their Implementations with VLSI

Sponsor: National Science Foundation of China

Duration: From Jan. 2006 to Dec. 2008

ID number: 60576027

Manager: BAI Guoqiang

In this project, various efficient implementation methods and algorithms of ECC will be investigated, particularly a focus on structures of algorithms and architectures both are suitable for VLSI implementations of ECC is stressed.It includes two aspects of tasks as following. Firstly, attempt to develop noval algorithms and approaches to ECC implementation, or to improve those of existed algorithms and approaches for the purpose of better satisfying the diverse requirements of different VLSI implementations. Secondly, according to different design goals and based on the developed or improved algorithms, propose noval algorithmic structures and architectures in VLSI implementations and to obtain experiment results and data of those VLSI implementations. Key problems expected to be solved in this project are arosed from the process of a development of a high-performanec ECC chip under taken by the applicant in recent years. Achievements resulted from this project are expected to enrich the theory, practice and experiment results on VLSI implementation of ECC and to support researches and developments of chips that can implement national ECC standard.

(15)Researches of VLSI Implementation Technologies for Elliptic Curve Cryptosystems and Cryptographic Hash Functions

Sponsor: The High Technology Program of the Ministry of Science and Technology

Duration: From Dec. 2006 to Dec. 2008

ID number: 2006AA01Z415

Manager: BAI Guoqiang

This project mainly study the theory, the technologies and the methods of when the elliptic curve cryptosystems and the cryptographic hash functions are implemented by VLSI. It will include the algorithmic structures,the circuit architectures and the implementation methods for the low level finite arithmetics of ECC and the high system level of ECC，respectively. It also includes the circuit architectures and the implementation methods of the cryptographic hash functions.