Solid-State Devices and Integration Technologies Division

1. Introduction
The solid-state devices and integration technologies research division mainly researches on the ULSI integration process and process modules, the Silicon-based special application solid-state devices and integration technologies. The division has an industrial ULSI process pilot line, which is the first and sole IC process line in the universities in mainland of China and is an important part of North Microelectronics R&D Base, Beijing, China. The process line holds a complete set of 5-inch sub-micro CMOS process facilities, with the clean room space being about 960 m2 and the throughput higher than 50K wafers per year.

In 2007, the national education ministry approved the division start to establish the “Solid-State Devices and Integration Technologies” engineering research center, which will focus on the research on Si-based solid-state devices and special utilization IC technologies and will build an open researching platform for novel materials, devices, processes, circuitries and equipments. The center will also dedicate to develop a series of industrial technologies, such as the novel non-volatile memories, SiGe microwave and power devices, SiGe/Bi-CMOS process and RF circuits, and come to be the research base for IC technologies and education base for high-level micro-electronics students.

The division also focuses on the cooperation with oversea and domestic semiconductor companies, universities and research institutes. Among these companies, IBM, Motorola, Applied-Material and ASML had donated more than 20 sets of semiconductor fabrication equipments to support the R&D and education programs in the division; ASML simultaneously cooperated with us to conduct a “Joint Application Research Program” in 2004. In 2004, the division cooperated with Chinese Electronic and Information Industry Group and invested 9.5M USD to establish the CEC Hua-Qing Microelectronics Engineering Center.

In 2007, there are 1 professor, 10 associate professors, 16 lecturers or engineers and 2 post-doctor in the division. There are also 24 master candidates and 5 Ph. D candidates in the division.

1.1 Staff

Director

Pan Liyang

Tel: (86)-(10)-62789192

Email: panly@tsinghua.edu.cn

Vice-director:

Wang Jing

Tel: (86)-(10)-62789152

Email: wang_j@tsinghua.edu.cn

1.2 Clean Room

The division has more than 800 M2 clean room space, among which, there is 100 M2 Class 10 clean room space and 700 M2 Class 100-1000 clean room space.

1.3 Key Equipment

•  Epitaxy: AM Epicentura-200, SGE 500/400

•  Stepper: Nikon 1505i 7A , Nikon 1505G 4D, ASML 2000B, ASML 5500-100

•  Projector: Perkin-Elmer 500HT

•  Dry etcher: AME 8300, Tegal511e

•  Ion implanter: Varian 350D, Eaton NV 1080

•  Sputter: Varian 3190,MTI

•  Instruments: HP 4062B, HP 4284, HP 4145, Keithley-4200-SCS, On-line SEM S7000

2. Main R&D Fields

(1)1. Research on ULSI integration process and process modules

•  Research on the Advanced IC Process Module Technologies

•  Material and Process

•  Special type semiconductor process and integration

•  Virtual fabrication and automatic controlling system for IC manufacture

(2) Research on novel micro/nano-meter devices and materials

•  Novel micro/nano-meter materials and high-K materials

•  Strained-Silicon, Strained SiGe on Insulator (SGOI), and Germanium channel engineering

•  Novel structures and characteristics for nm-scale devices

•  Devices, processes and integration technologies for novel micro/nano-meter devices

(3) Research on SiGe high frequency devices and microwave IC

•  High Performance SiGe UHV/CVD epitaxy system, material and process

•  Selective Epitaxy Process and Self-Align Process Module

•  GHz microwave SiGe HBT and Power HBT Technologies

•  Integration process of RF SiGe-BiCMOS

•  RF circuits based on SiGe processes

(4)Research Fields of non-Volatile Semiconductor Memory Technologies

•  Devices, processes and circuits for EEPROM/Flash memories

•  Materials, devices, processes and circuits for SONOS and charge-trapping memories

•  Materials, devices and circuits for Nano-Crystal Memory

•  Pure CMOS process based NVRAM

•  Devices, processes and circuits for embedded flash memories

•  Anti-radiation non-volatile memories

(5)Research on high voltage high power devices and power-integrated technologies

•  Novel structures, devices and process technologies of high voltage and Power Devices

•  Research and technical service on high voltage power VDMOS and RF LDMOS devices

•  Integration Process of CMOS and High Voltage and Power Devices

•  Integration of Novel CMOS-Bipolar-SCR Process and Circuit Design

(6)Research on special IC equipments and equipment related process technologies

•  Technologies and processes for special IC equipments

•  SiGe UHV-CVD system and epitaxial technologies

•  RTP and laser annealing equipment

3. Main R & D Achievements and Projects

There are total 18 research projects undertaken by IC process division in 2005.

(1) Name: Research on the technologies of novel low voltage and low power Flash memory

Sponsor: National Nature and Science Foundation

Manager: Pan Liyang

Duration: 2004-2006

Traditional stacked-gate Flash memory cells mainly use FN tunneling or CHEI (Channel Hot Electron Injection) mechanisms to perform programming, resulting in high program voltage, low speed and large power. These problems make Flash memory operated in high voltage and difficult to be scaled-down, therefore limit its further development. This project firstly proposed a novel low voltage and low power Flash memory technology programmed with source induced band-to-band tunneling hot electron injection, whose programming speed is 10μs, programming current and power are 2.5μA and 15?W, respectively, and read current can get up to 150μA at 3.3V access voltage. By the research on its cell structure, programming characteristics, integration process and reliability, the SIBE flash memory cell is demonstrated to have lower program voltage, smaller power consumption, higher program speed and higher access speed, and good reliability and convergency. Owning to its lower source-to-drain punch-through effect and program current, the memory cell is easier to be scaled-down and integrated with the system. The merits make the proposed SIBE flash have good potential to be used in low voltage and low power Code storage utilizations.

(2) Name: Fundamental research on next-generation super-high speed strained silicon MOS devices and circuits

Sponsor: National Nature and Science Foundation

Manager: Jun Xu

Duration: 2005-2007

The project aims to research on growth method and process for high-quality strained Si material, and develop low temperature stressed CMOS compatible process for strained Silicon MOS devices. The project will also research on the mobility, the effect of channel doping and temperature, and device characteristics of strained Silicon MOS devices.In 2005, we have fabricated strained Si/Si0.7Ge0.3/graded Si1-xGex/Si substrate multilayer structure using a production-compatible reduced pressure chemical vapor deposition system, where in the graded Si1-xGex layer the Ge mole fraction x gradually increases from 0 to 20%. The properties of the multilayer structure was evaluated using different analysis instruments, the results have shown that the root mean square surface roughness is 4.125nm, the strain in the strained cap Si layer is about 1.2%, and the threading dislocation density is about 2′104cm-2. Further rapid thermal annealing experiment demonstrated that the stress in the strained cap Si layer is stable suffered from the thermal budget in the later device fabrication process.

(3) Name: Research on the gate and channel engineering technologies for sub-65nm CMOS devices

Sponsor: National Nature and Science Foundation (key project)

Manager: Jun Xu

Duration: 2006-2009

This project will focus on the research of new theory and new technology related to the integration technology of channel and gate engineering based on the stained silicon, high-k dielectric materials and metal gate electrodes etc. This research will establish the foundation for developing the VLSI technology with ourselves intellectual property. The research included: (1) Epitaxial grow the single crystal silicon germanium, relaxed silicon germanium, strained silicon materials and optimize the corresponding technology. Develop the integration technology of channel engineering based on the silicon germanium and strained silicon. (2) Investigate high-k dielectrics for new gate structure application and characterize reliability properties. Study the interfacial properties in the channel and gate structures. (3) Explore the integrated CMOS technology suitable for 65 nm generation based on the high mobility channel materials, high-k gate dielectrics and metal gate electrodes. Optimize the new CMOS structure and develop the theory model. This project will solve the critical fundamental problem of channel and gate engineering of CMOS at 65 nm and below generation. Moreover, this project will provide the guide at the theory and experiment for the realization of next generation CMOS devices and circuits with good performance.

(4) Name: Research on low power and high reliable non-volatile memory devices

Sponsor: National Basic Research Program of China

Manager: Xu Jun

Duration: 2006-2010

Aiming to solve the technical problems and limitations for the traditional scaled non-volatile memory devices, this project mainly researches on the materials, devices and technologies for charge trapping memory, nano-crystal memory and RRAM. Through the study and research on novel high-K storage materials, novel memory device structures, nano-meter materials and corresponding theories and some basic process technologies, the project will try to develop Giga-density NVSM technologies for next-generation low voltage and low power utilizations.

(5) Name: Producing of high performance SiGe based microwave devices and ICs

Sponsor: National Development and Reform Commission.

Manager: Liu Zhihong, Yan Liren

Duration: 2006-2007

The project was carried out by CEC Huaqing Microelectronics Co. Ltd. and Institute of Microelectronics of Tsinghua University. It has been finished in the end of 2007. Achievements of this project have been checked and accepted in January, 2008. When the project started in January 2007, the equipment and technology for growing SiGe epitaxial layers was ready, also some prototype SiGe HBT device samples were obtained with self-developed techniques. More production machines, especially some microwave measurement instruments, were reinforced during the project period. Further, unit process technologies such as selective SiGe epitaxial, DTI, double metal process, were developed. With all these improvements in facilities and technologies, our SiGe devices/ICs has been promoted form prototype phase to production phase. The SiGe HBT ft frequency has been successfully increased from the original 5-6GHz to 20GHz. Now the production capacity for SiGe devices/ICs is 1000 wafers per month. By the end of 2007, totally over 10 Million SiGe HBTs has been produced, of which 8 Million HBTs has been sold to market.

(6) Name : Research on Novel Nano-meter Scale High Density Charge-Trapping Memory

Sponsor: Basic Research Foundation of Tsinghua National Laboratory for Information Science and Technology (TNList)

Manager: Pan Liyang

Duration: 2006-2007

Based on the research on the process and conduction of the high-K materials, such as the HfO2 trapping layer, Al2O3 blocking layer and the multilayer gate stack in the charge-trapping memory devices, the project aims to propose novel device structure and operation mechanisms for nano-meter scale high density CTM utilization. In 2007, the project successfully developed a prototype of the proposed CTM device, and research on its trapping/detrapping characteristics, charge distribution/redistribution, program and reliability characteristics.

(7) Name: Research on germanium material and device with high channel mobility

Sponsor: Basic Research Foundation of Tsinghua National Laboratory for Information Science and Technology (TNList)

Manager: Wang Jing

Duration: 2006-2007)

Strained germanium (Ge) has become more and more promising as an alternative channel material because of its excellent mobility performance. In this project, a relaxed SiGe buffer layer was epitaxial grown on silicon substrate by reduced-pressure chemical vapor deposition (CVD) technique, and then a biaxial strained Ge film and a strained silicon cap were deposited by ultra-high vacuum CVD. The Ge content in the SiGe buffer layer determines the stress in Ge film. Strained Ge MOSFET was fabricated with a SiO2 gate dielectric. The project will provide a lot of basic experimental data for further R&D on strained Ge material and device.

(8) Name: Research on the Nano-Crystal Non-Volatile Memory

Sponsor: Basic Research Foundation of Tsinghua National Laboratory for Information Science and Technology (TNList)

Manager: Zhang Zhigang

Duration: 2007-2008

Introduction: The Research of Nanocrystal Non-volatile memories focuses on the nanocrystal materials deposition, devices integration, new structure design, as well as the optimization of the related technology. During 2006 – 2007, the deposition technologies of silicon and metal nanocrystal materials were developed based on electron evaporation etc. Nanocrystal non-vilatile devices contained single and multi-layer silicon nanocrystals were processed on our standard sub-micro CMOS polit-line, and the properties of program/erase and reliability have been studied systematically. Also, the mechanism of charge transfer and storage has been developed.

(9) Name: 4bit High Speed Error Check and Correction Circuit (ECC) for next-generation 32nm NOR Flash

Sponsor: International Cooperation

Manager: Pan Liyang

Duration: 2007-2008

With the shrinking of the feature size, increasing of the error rate and requirement of the multi-level technique for next--generation Giga-Bit NOR Flash, the project aims to develop 4bit high speed Error Check and Correction Circuit (ECC) for 32nm NOR Flash utilization, cooperated with world-level Flash company. Through the research on the arithmetic, mathematics, system architecture and circuitries, the project successfully developed a 4Bit/512Bit 12ns ECC with 1.3mm2 area penalty.

(10) Name: JARP-Joint Application Research Program on Lithography Technologies cooperated with ASML Co., Netherlands.

Sponsor: Economic Ministry of Netherlands

Manager: Yan Liren

Duration: 2002-2008

With the fund support from Economic Ministry of Netherlands, ASML will donate two sets of lithography equipment to IMETU. In 2003, the first set of ASML2500/40 had been successfully built in, and used for research on lithography technology, high voltage device and EEPROM process. The other set of ASML5500/100D was also set up in 2004. In 2005, the ASML5500/100D was successfully debugged for the product and research utilization. Simultaneously, the all-around cooperation between ASML and IMETU was started to research on SiGe HBT device, non-volatile memory devices, RF MEMS and process development knowledge.

(11) Name: Digital Read-Out Integrated Circuit for Integrated Infrared Sensors

Sponsor : Industry cooperation

Manager: Xu Jun, Wu Dong

Duration: 2006-2008

This project is focused on the digital read-out integrated circuit for integrated infrared sensors. The research topics include: low-noise design, low temperature design, low power and high precise ADC design. The triple-slope ADC circuit has been successfully developed in 2007, and a novel ∑Δ ADC is under developing now.

4.Achievements and Publications:

In 2007, this division published 17 papers, including of 1 international journal paper, 6 domestic journal papers and 4 international proceeding papers. There are also 1 patent granted and 5 patents applied in the past year.